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mic7400 configurable pmic, five - channel buck regulator plus one - boost with hyperlight load ? and i 2 c control hyperlight load is a registered trademark of micrel, inc . micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com march 3, 2015 revision 2.0 general description th e mic7400 is a powerful, highly integrated, configurable, power - management ic (pmic) featuring five synchronous buck regulators, one boost regulator and high - speed i 2 c interface with an internal eeprom. the device offers two distinct modes of operation ?stand - by mode? and ?normal mode? intended to provide an energy optimize d solution suitable f or portable handheld, and infotainment applications. in normal mode, th e programmable switching converters can be configured to support a variety of features, including start - up sequencing, timing, soft - start ramp, output voltage levels, current limit levels and output discharge for each channel. in stand - by mode the pmic can configured in a low power state by either disabling an output or by chan g ing the ou tput voltage to a lower level. independent exit from stand - by mode can be achieved either by i 2 c communication or the external stby pin. the device has five synchronous bu ck regulators with high - speed adaptive on - time control supporting even the challenging ultra - fast transient requirement for core supplies. one boost regulator provides a flash - memory programming supply that delivers up to 200ma of output current. the boost is equipped with an output disconnect switch that opens if a short - to - ground fault is detected. an internal eeprom enables a single - chip solution across many platforms by allowing the designer to customize the pmic for their design. modifications can be made without the need to re - approve a new pmic, saving valu able design resources and time. all switchers provide light - load efficiency with hyperlight load ? mode for buck and pfm mode for boost. an additional benefit of this proprietary architecture is ver y - low output ripple voltage throughout the entire load range with the use of small output capacitors. the mic7400 is designed for use with a small inductor s (down to 0.47h for buck, 1.5h for boost), and an output capacitor as small as 10f for buck, enab ling a total solution size of 15mm 15mm and less than 1mm height. the datasheet and other support documentati on can be found on micrel?s web site at: www.micrel.com . features ? input v oltage: 2.4 v to 5.5v ? five independen t synchronous bucks up to 3a ? one independent non - synchronous boost 200ma ? 200a quiescent current (all regulators on) ? 93% peak buck efficiency, 85% typical efficiency at 1ma ? dual power mode: stand - by and normal mode ? i2c interface up to 3.4mhz ? i2c on - the - fly eeprom programmability , featuring: ? buck and boost output voltage scaling ? power - on - reset threshold and delay ? power - up sequencing / sequencing delay ? buck and boost current limit ? buck and b oost pull - down when disabled ? individual on, off, and standby modes ? soft - start and g lobal power - good masking ? 23a buck typical quiescent current ? 70a boost typ ical quiescent current ? 1.5% output accuracy over temperature/line/load ? 2.0mhz boost switching frequency ? 1.3 mhz buck operation in continuous mode ? ultra - fast buck transient response ? 15mm 15mm 1.25mm solution size ? thermal - shutdown and current - limit protection ? 36- pin 4.5mm 4.5mm 0.85mm fqfn package (0.4 mm pitch ) ? ? 40 c to +125 c junction temperature range applicatio ns ? c lient and enterprise solid state d rives (ssd) ? consumer and in - vehicle infotainment devices ? multimedia devices ? portable handheld devices ? security camera ? gaming machines ? service provider gateways
micrel, inc. mic7400 march 3, 2015 2 revision 2.0 typical application ordering information part number marking output voltages features package ( 1 ) lead finish MIC7400YFL 7400 ywws 1.8v, 1.1v, 1.8v 1.05v, 1.25v, 12v stby ? active low falling edge ( default ) 36- pin 4.5mm 4.5mm fqfn pb - free mic7400 -xxxx yfl ( 2 ) x x 7400 x yyww x configurable configurable 36- pin 4.5mm 4.5mm fqfn pb - free note s : 1. green, rohs - compliant package. lead finish is matte tin. mold compound is halogen free . 2. configurable options available upon request. contact marketing .
micrel, inc. mic7400 march 3, 2015 3 revision 2.0 table of contents list of figures .......................................................................................................................................................................... 5 list of tables ........................................................................................................................................................................... 6 pin configuration ..................................................................................................................................................................... 7 pin de scription ........................................................................................................................................................................ 7 absolute maximum ratings .................................................................................................................................................. 10 operating ratings ................................................................................................................................................................. 10 electrical characteristics ....................................................................................................................................................... 10 typical characteristics .......................................................................................................................................................... 15 functional characteristics ..................................................................................................................................................... 17 mic7400 block diagram ....................................................................................................................................................... 24 functi onal description ........................................................................................................................................................... 25 programmable buck soft - start control ............................................................................................................................. 25 buck digital voltage control (dvc) ................................................................................................................................... 26 programmable boost soft - start control ............................................................................................................................ 27 boost digital voltage control (dvc) ................................................................................................................................. 28 buck current limit ............................................................................................................................................................. 28 boost current limit ............................................................................................................................................................ 29 global power good pin ..................................................................................................................................................... 29 standard delay .................................................................................................................................................................. 29 power - up sequencing ....................................................................................................................................................... 29 programmable power - on- reset (por) delay .................................................................................................................. 30 power - down sequencing .................................................................................................................................................. 30 stand - by mode .................................................................................................................................................................. 31 resistive disc harge ........................................................................................................................................................... 31 stby pin ........................................................................................................................................................................... 31 safe start - up into a pre - biased output ............................................................................................................................ 32 buck regulator power dissipation .................................................................................................................................... 32 total power dissipation ..................................................................................................................................................... 32 powe r derating .................................................................................................................................................................. 33 overtemperature fault ...................................................................................................................................................... 33 thermal measurements ..................................................................................................................................................... 34 timing diagrams ................................................................................................................................................................... 35 normal power - up sequence for outputs .......................................................................................................................... 35 standby (stby) pin (wake - up) ............................................................................................................................................ 36 evaluation board schematic ................................................................................................................................................. 37 bill of materials ...................................................................................................................................................................... 38
micrel, inc. mic7400 march 3, 2015 4 revision 2.0 table of contents (continued) pcb layout guidelines general .............................................................................................................................................................................. 39 ic ....................................................................................................................................................................................... 39 input capacitor .................................................................................................................................................................. 39 inductor .............................................................................................................................................................................. 39 output capacitor ............................................................................................................................................................... 39 proper termination of unused pins ...................................................................................................................................... 40 pcb layout recommendations ............................................................................................................................................ 41 pa ckage information and recommended landing pattern .................................................................................................. 45 appendix a ............................................................................................................................................................................ 46 i 2 c control register ........................................................................................................................................................... 47 serial port operation ......................................................................................................................................................... 47 extern al host interface .................................................................................................................................................. 47 special host i 2 c commands ......................................................................................................................................... 48 special keys .................................................................................................................................................................. 48 appendix b ............................................................................................................................................................................ 49 register settings descriptions .......................................................................................................................................... 49 power good register (00?h) .......................................................................................................................................... 49 eeprom - ready register (01?h) ................................................................................................................................... 50 fault registers (02?h) ..................................................................................................................................................... 51 standby register (03?h) ..................................................................................................................................................... 52 enab le/disable register (04?h) .......................................................................................................................................... 53 regulator output voltage setting normal mode (05?h ? 09?h) ...................................................................................... 54 boost regulator output voltage setting normal mode (0a?h) ...................................................................................... 55 regulator voltage setting stby mode (0b?h ? 0f?h) ....................................................................................................... 56 boost regulator output voltage setting stby mode (10?h) ............................................................................................. 57 sequence register (11?h) .................................................................................................................................................. 58 delay register (17?h) ......................................................................................................................................................... 61 soft - start registers (18?h ? 1a?h) ...................................................................................................................................... 62 current - limit (normal mode) registers (1b?h ? 1d?h) ...................................................................................................... 63 current - limit (stby mode) registers (1e ? 20?h) ............................................................................................................ 65 power - on - reset (por) threshold voltage setting register (21?h and 22?h) ................................................................... 66 pull - down when disabled register (23?h) ......................................................................................................................... 67
micrel, inc. mic7400 march 3, 2015 5 revision 2.0 list of figures figure 1. buck soft - start ..................................................................................................................................................... 25 figure 2. buck soft - start ..................................................................................................................................................... 26 figure 3. buck dvc control ramp ..................................................................................................................................... 26 figure 4. buck dvc control ramp ..................................................................................................................................... 27 figure 5. boost soft - start ramp ......................................................................................................................................... 27 figure 6. boost soft - start .................................................................................................................................................... 27 figure 7. boost dvc control ramp .................................................................................................................................... 28 figure 8. standard delay time ........................................................................................................................................... 29 figure 9. hot plug ? v in rising ........................................................................................................................................... 30 figure 10. por ..................................................................................................................................................................... 30 figure 11. hot un - plug ? v in falling ..................................................................................................................................... 30 figure 12. i 2 c stand - by mode .............................................................................................................................................. 31 figure 13. output pull - down resistance .............................................................................................................................. 31 figure 14. stby - to - normal transition (default) .......................................................................................................... 32 figure 15. pre - biased output voltage .................................................................................................................................. 32 figure 16. power dissipation ................................................................................................................................................ 33 figure 17. power derating curve .......................................................................................................................................... 33 figure 18. hot plug input voltage spike ............................................................................................................................... 34 figure 19. mic7400 power - up/down ................................................................................................................................... 35 figure 20. mic7400 stby function (default) ................................................................................................................. 36 figure 21. conne ctions for unused pins .............................................................................................................................. 40 figure 22. read/write protocol ............................................................................................................................................. 47
micrel, inc. mic7400 march 3, 2015 6 revision 2.0 list of tables table 1. buck outputs default soft - start time (default) ................................................................................................. 26 table 2. boost output default soft - start time ..................................................................................................................... 28 table 3. buck current limit register settings ...................................................................................................................... 28 table 4. summarization of unused pin connections ........................................................................................................... 40 table 5. power good status register .................................................................................................................................. 49 table 6. eeprom status register ....................................................................................................................................... 50 table 7. overcurrent status fault register .......................................................................................................................... 51 table 8. standby register ..................................................................................................................................................... 52 table 9. enable register ....................................................................................................................................................... 53 table 10. dvc registers for out[1 ? 5] .............................................................................................................................. 54 tabl e 11. dvc registers for out6 ....................................................................................................................................... 55 table 12. standby registers ................................................................................................................................................. 56 table 13. standby dvc register for out6 .......................................................................................................................... 57 table 14. sequence state 1 register ................................................................................................................................... 59 table 15. sequ ence state 2 register ................................................................................................................................... 59 table 16. sequence state 3 register ................................................................................................................................... 59 table 17. sequence state 4 register ................................................................................................................................... 60 table 18. sequence state 5 register ................................................................................................................................... 60 table 19. sequence state 6 register ................................................................................................................................... 61 table 20. delay register ....................................................................................................................................................... 61 table 21. soft - start register speed settings ....................................................................................................................... 62 table 22. soft - start register out1 and out2 .................................................................................................................... 62 table 23. soft - start register out3 and out4 .................................................................................................................... 62 table 24. soft - start register out5 and out6 .................................................................................................................... 63 table 25. current - limit register i out1 and i out2 ................................................................................................................... 63 table 26. current - limit register i out3 and i out4 ................................................................................................................... 64 table 27. current - limit register i out 5 and i out6 ................................................................................................................... 64 table 28. standby current - limit register i out1 and i out2 ..................................................................................................... 65 table 29. standby current - limit register i out3 and i out4 ..................................................................................................... 65 table 30. standby current - limit register i out5 and i out6 ..................................................................................................... 66 table 31. rising and falling power - on- reset threshold voltage settings .......................................................................... 66 table 32. power - on- reset rising threshold voltage setting register (21?h) ...................................................................... 67 table 33. power - on- reset falling threshold voltage setting register (22?h) ..................................................................... 67 table 34. pull - down when disabled register ....................................................................................................................... 67
micrel, inc. mic7400 march 3, 2015 7 revision 2.0 pin configuration 36- pin 4.5mm 4.5mm fqfn ( fl ) (top view) pin description pin num ber pin name description 1 sw2 switch pin 2 (output): inductor connection for the synchronous step - down regulator. connect the inductor between the output capacitor and the sw2 pin . 2 pvin2 power supply voltage 2 (input): input supply to the source of the internal high - side p - channel mosfet. a n input capacitor between pvin2 and the power ground pgnd2 pin is required and to be place d as close as possible to the ic. 3 out2 output voltage sense 2 (input): this pin is used to sense the output voltage. connect out2 as close to the output capacitor as possible to sense output voltage. also provides the path to discharge the output through an internal 90 resistor when disabled. this pull - down feature is programmed through the pulld[x] register. 4 pvin3 power supply voltage 3 (input): inpu t supply to the source of the internal high - side p - channel mosfet. an input capacitor between pvin3 and the power ground pgnd3 pin is required and to be place d as close as possible to the ic. 5 sw3 switch pin 3 (output): inductor connection for the synchronous step - down regulator. connect the inductor between the output capacitor and the sw3 pin . 6 pgnd3 power ground 3: the power ground for the synchronous buck converter power stage. the pgnd pin connects to the sources of the internal low - side n - channel mosfet, the negative terminals of input capacitors, and the negative terminals of output capacitors. 7 out3 output voltage sense 3 (input): this pin is used to sense the output voltage. connec t out3 as close to the output capacitor as possible to sense output voltage. also provides the path to discharge the output through an internal 90 resistor when disabled. this pull - down feature is programmed through the pulld[x] register. 8 pvin4 power supply voltage 4 (input): input supply to the source of the internal high - side p - channel mosfet. an input capacitor between pvin4 and the power ground pgnd4 pin is required and to be place d as close as possible to the ic.
micrel, inc. mic7400 march 3, 2015 8 revision 2.0 pin description (continued) pin num ber pin name description 9 sw4 switch pin 4 (output): inductor connection for the synchronous step - down regulator. connect the inductor between the output capacitor and the sw4 pin . 10 pgnd4 power ground 4: the power ground for the synchronous buck converter power stage. the pgnd pin connects to the source of the internal low - side n - channel mosfet, the negative terminals of input capacitors, and the negative terminals of output capacitors. 11 out4 output voltage sense 4 (input): th is pin is used to sense the output voltage. connect the out 4 as close to the output capacitor as possible to sense output voltage. also provides the path to discharge the output through an internal 90 resistor when disabled. this pull - down feature is prog rammed through the pulld[x] register. 12 stby standby reset (input): standby mode allows the total power consumption to be reduced by either lowering a supply voltage or turning it off. the ic can be placed in standby mode while operating in n ormal mode b y a high -to - low transition ( default ) on the stby input. when this occurs , the stby_modeb bit will be set to logic ? 0 ?. either a low -to - high transition on the stby pin or an i2c write command to the stby_modeb bit sets a ll of the regulators to their normal mode default settings. this pin can be driven with either a digital signal or open collector output. do not let this pin float. connect to ground or v in . a pull - down resistor of 100 k or less can also be used . there are both a high -to - low ( default ) and low -to - high normal to standby trigger options available. 13 sda high - speed mode 3.4mhz i2c data (input/output): this is an open drain , bidirectional data pin. data is read on the rising edge of the scl and data is clocked out on the falling edge of the scl. external pull - up resistors are required. 14 agnd analog ground: internal signal ground for all low power circuits. connect to ground plane for best operation. 15 scl high - speed mode 3.4mhz i2c clock ( input ): i2c serial clock line open drain in put. external pull - up resistors are required. 16 por power -o n - reset (output): this is an open drain output that goes high after the por delay time elapses. the por delay time starts as soon as the avin pin voltage rises above the upper threshold set by the porup register. the por output goes low without delay when avin falls below the lower threshold set by the pordn register. 17 out5 output voltage sense 5 (input): this pin is used to sense the output voltage. connect out 5 as close to the output capac itor as possible to sense output voltage. also provides the path to discharge the output through an internal 90 resistor when disabled. this pull - down feature is programmed through the pulld[x] register. 18 pgnd5 power ground 5: the power ground for the synchronous buck converter power stage. the pgnd pin connects to the source of the internal low - side n - channel mosfet, the negative terminals of input capacitors, and the negative terminals of output capacitors. 19 sw5 switch pin 5 (output): inductor connection for the synchronous step - down regulator. connect the inductor between the output capacitor and the sw5 pin . 20 pvin5 power supply voltage 5 (input): input supply to the source of the internal high - side p - chann el mosfet. an input capacitor between pvin5 and the power ground pgnd5 pin is required and to be place d as close as possible to the ic. 21 out6 output voltage 6 sense (input): this pin is used to sense the output voltage. connect out 6 as close to the output capacitor as possible to sense output voltage. also provides the path to discharge the output through an internal programmable current source when di sabled. this pull - down feature is programmed through the pulld[x] register. 22 pgnd6 power ground 6: the power ground for the boost converter power stage. the pgnd pin connects to the source of the internal low - side n - channel mosfet, the negative terminals of input capacitors, and the negative terminals of output capacitors. 23 sw6 swit ch pin 6 (input): inductor connection for the boost regulator. connect the inductor between the pvin6o and sw6 pin .
micrel, inc. mic7400 march 3, 2015 9 revision 2.0 pin description (continued) pin num ber pin name description 24 pvin6o power supply voltage 6 (output): this pin is the output of the power disconnect switch for the boost regulator. when the boost regulator is on, an internal switch provides a current path for the boost inductor. in shutdown, an internal p - channel mo sfet is turned off and disconnects the boost output from the input supply. this feature eliminates current draw from t he input supply during shutdown. an input capacitor between pvin6 o and the power ground pgnd6 pin is required and place as close as possible to the ic. 25 pvin6 power supply voltage 6 (input): input supply to the internal disconnect switch . 26 pvin1 power supply voltage 1 (input): input supply to the source of the i nternal high - side p - channel mosfet. an input capacitor between pvin1 and the power ground pgnd1 pin is required and to be place d as close as possible to the ic. 27 sw1 switch pin 1 (output): inductor connection for the synchronous step - down regulator. connect the inductor between the output capacitor and the sw1 pin . 28 pgnd1 power ground 1: the power ground for the synchronous buck converter power stage. the pgnd pin connects to the source of the internal low - side n - channel mosfet, the negative terminals of input capacitors, and the negative terminals of output capacitors. 29 out1 output voltage sense 1 (input): this pin is used to sense the output voltage remotely . connect out 1 as close to output capacitor as possible to sense output voltage. this feature a lso provides the path to discharge the output through an internal 90 resistor when disabled. the pull - down feature is programmed through the pulld[x] register. 30 vslt por selection threshold (input): a high on this pin sets the porup and pordn registers to their upper threshold limits and a low to their lower threshold limits. do not leave floating. 31 avin analog voltage supply (input): the start - up sequence begins as soon as the avin pin voltage rises above the ic?s uvlo upper threshold. the outputs do not turn off until avin pin voltage falls below the lower threshold limit. a 2.2 f ceramic capacitor from the avin pin to agnd pin must be placed next to the ic. 32 agnd analog ground: internal signal ground for all low power circuits. connect directly to the layer 2 ground plane. layer 2 is the point where all the pgnds and agnd are connected. do not connect pgnd and agnd together on the top layer. 33 nc no connect. must be left floating. 34 nc no connect. must be left floating. 35 pg global power good (output): this is an open drain output that is pulled high when all the regulator power good flags are high. if an output falls below the power good threshold or a thermal fault occurs, the global power good flag is pulled low. there is a falling edge de - glitch time of 50s to prevent false triggering on output voltage transients. a power good mask feature programmed through the pgood_mask[x] registers can be used to ignore a power good fault. when masked an individual power good fault wil l not cause the global power good output to de - assert. do not connect the power good pull - up resistor to a voltage higher than av in . 36 pgnd2 power ground 2: the power ground for the synchronous buck converter power stage. the pgnd pin connects to the sou rce of the internal low - side n - channel mosfet, the negative terminals of input capacitors, and the negative terminals of output capacitors . ep epad exposed pad: must be connected to the gnd plane for full output power to be realized .
micrel, inc. mic7400 march 3, 2015 10 revision 2.0 absolute maximum ratings ( 3 ) supply voltage s ( p v i n[1 - 6] ) .................................. - 0.3v to 6 v analog supply voltage ( a v i n ) ............................ - 0.3v to 6 v buck output voltage s (v out [1- 5] ) ......................... - 0.3v to 6 v boost output voltage (v out 6 ) ........................... - 0.3v to 20 v buck switch voltage s (v sw [1 - 5] ). ......................... - 0. 3 v to 6v boost switch voltage (v sw 6 ). ........................... - 0. 3 v to 20v power good voltage (v pg ) .............................. - 0.3v to a v in power - on reset output (v por ) .......................... - 0.3v to 6v por threshold voltage (v vslt ) ......................... - 0.3v to 6v standby voltage (v stby ) ..................................... - 0.3v to 6v i2c io (v sda , v scl ) ........................................... - 0.3v to a v in agnd to pgnd[1 - 6] ....................................... - 0.3v to 0.3 v ambient storage temperature (ts) ........... - 40 c to +150c esd hbm rating (6) ........................................................ 2kv esd mm rating ............................................................ 200v operating ratings ( 4 ) input voltage ( p v in [1 - 6] ) ..................................... 2.4 v to 5.5v analog input voltage ( a v in ) ............................. 2.4 v to 5.5v buck output voltage range (v out[1 - 5] ) ............. 0.8 v to 3.3v boost output voltage range (v out6 ) ................... 7 v to 14v power good voltage (v pg ) ................................... 0 v to a v in power - on reset output (v por ) ............................ 0v to a v in por threshold voltage (v vslt ) ........................... 0 v to a v in standby voltage (v stby ) ....................................... 0 v to a v in i2c io (v sda , v scl ) ................................................ 0 v to a v in junction temperature (t j ) (5 ) ...................... - 40c to + 125 c junction thermal resistance 4.5 mm 4.5 mm fqfn - 36 ( ja ) ........................ 30c/w electrical characteristics ( 7 ) v in = av in = pv in (1 - 6) = 5.0v; v out1 = 1.8v; v out2 = 1.1v; v out3 = 1.8v; v out4 = 1.05v; v out5 = 1.25v; v out6 = 12v (refer to the evaluation board schematic for component values). t a = 25c, unless otherw ise noted. bold values indicate ? j ??& parameter conditions min . typ . max . unit input supply (vin) input voltage range ( av in , pv in[1 - 6] ) 2.4 5.5 v operating qu iescent current into av in ( 8 , 9 ) v in = 5.0v; i out = 0a 200 240 $ operating qu iescent current into pv in ( 8 ) v in = 5.0v; i out = 0a 0.3 1 $ under v oltage lockout threshold av in rising 2.15 2.25 2.35 v under voltage lockout hystere sis 150 mv standby input ( stby ) logic level high 1.2 v logic level low 0.4 v bias current into pin v stby = v in 200 na bias current out of pin v stby = 0v 200 na rising /falling edge reset deglitch 100 v notes: 3. absolute maximum ratings indicate limits beyond which damage to the component may occur. 4. the device is not guaranteed to function outside its operating rating. 5. the maximum allowable power dissipation is a function of the maximum junction temperature, t j(max) , the junction - to - ambient thermal resistance, ja , and the ambient temperature, t a . the maximum allowable power dissipation will result in excessive die temperature, and the regulator will go into thermal shutdown . 6. devices are esd sensitive. handling prec dxwlrqvuhfrpphqghg+xpdqerg\prghon lqvhulhvzlwks) 7. specification for packaged product only. 8. tested in a non - switching configuration . 9. when all outputs are configured to the minimum programmable voltage .
micrel, inc. mic7400 march 3, 2015 11 revision 2.0 electrical characteristics ( 7 ) (continued) v in = av in = pv in (1 - 6) = 5.0v ; v out1 = 1.8v; v out2 = 1.1v; v out3 = 1.8v; v out4 = 1.05v; v out5 = 1.25v; v out6 = 12v (refer to the evaluation board schematic for component values). t a = 25c, unless otherwise noted. bold values indicate ? j ??& parameter conditions min . typ . max . unit por threshold input ( vslt ) logic level high 1.2 v logic level low 0.4 v bias current i nto p in v vsl t = v in 200 na bias current out of pin v vslt = 0v 200 na power -o n - reset ( por ) comparator por upper comparator range av in rising , v vslt = 0v 2.646 2.7 2.754 v por lower comparator range av in falling, v vslt = 0v 2.548 2.6 2.652 v por upper comparator range av in rising , v vslt = v in 3.626 3.7 3.774 v por lower comparator range av in falling, v vslt = v in 3.528 3.6 3.672 v power reset output ( por ) and timer por delay 18 20 22 ms por deglitch delay av in falling 50 v por output low voltage i por = 10ma (sinking) 75 400 mv por leakage current v por = 5.5v 200 na global power good output (pg) buck power good threshold voltage v out[1 - 5 ] rising 87 91 95 %v out buck hysteresis ( 10 ) v out[1 - 5] falling 4 %v out boost power good threshold voltage v out[ 6] rising 87 91 95 %v out boost hysteresis ( 10) v out[6] falling 380 mv power good output low voltage i pg = 10ma (sinking) 75 400 mv power good leakage current v pg = 5.5v 0.01 200 na power good de - glitch delay v out[1 - 6] falling 100 v output sequencing delay ( 10) 0.96 1 1.04 ms thermal protection thermal shutdown t j rising 160 c thermal hysteresis 20 c note : 10. guaranteed by design.
micrel, inc. mic7400 march 3, 2015 12 revision 2.0 electrical characteristics ( 7 ) (continued) v in = av in = pv in (1 - 6) = 5.0v ; v out1 = 1.8v; v out2 = 1.1v; v out3 = 1.8v; v out4 = 1.05v; v out5 = 1.25v; v out6 = 12v (refer to the evaluation board schematic for component values). t a = 25c, unless otherwise noted. bold values indicate ? j ??& parameter conditions min . typ . max . unit synchronous buck (v out1 - v out5 ) buck output voltage accuracy (out[1 - 5]) typical output voltage 1 accuracy ( 11) includes load, line , and reference ? 1.5% 1.5% % typical output voltage 2 accuracy ( 11) includes load, line , and reference ? 1.5% 1.5% % typical output voltage 3 accuracy ( 11) includes load, line , and reference ? 1.5% 1.5% % typical output voltage 4 accuracy ( 11) includes load, line , and reference ? 1.5% 1.5% % typical output voltage 5 accuracy ( 11) includes load, line , and reference ? 1.5% 1.5% % output voltage 1 accuracy ( 11 ) ? 1% 1% % output voltage 2 accuracy ( 11 ) ? 1% 1% % output voltage 3 accuracy ( 11 ) ? 1% 1% % output voltage 4 accuracy ( 11 ) ? 1% 1% % output voltage 5 accuracy ( 11 ) ? 1% 1% % load regulation i out = 10m a to i out(max) 0.1 % line regulation v in = 3.3 v to 5.0v 0.05 % buck soft - start soft - start (1 - 5) lsb ( 10, 12) 3.84 4 4.16 s/step buck internal mosfets high - side on - resistance v in = 3.3v; i sw[1 - 5] = 200ma 54 p? high - side on - resistance v in = 5.0v; i sw[1 - 5] = 200ma 40 p? low - side on- resistance v in = 3.3v; i sw[1 - 5] = - 200ma 37 p? low - side on- resistance v in = 5.0v; i sw[1 - 5] = - 200ma 30 p? output pull - down resistance v sw[1 - 5] = 0v 75 90 200 buck controller timing fixed on -t ime ( 13) v in = 3.3; v out = 1.0v; i out = 1.0a 220 ns minimum off -t ime 80 ns note : 11. not tested in a closed loop configuration. 12. the soft - start time is calculated using the following equation: t softstart = [(v out_program ? 0.15)/0.05 +1) t ramp . 13. buck frequency is calculated using the following equation f sw = (v out /v in ) (1/t on ).
micrel, inc. mic7400 march 3, 2015 13 revision 2.0 electrical characteristics ( 7 ) (continued) v in = av in = pv in (1 - 6) = 5.0v ; v out1 = 1.8v; v out2 = 1.1v; v out3 = 1.8v; v out4 = 1.05v; v out5 = 1.25v; v out6 = 12v (refer to the evaluation board schematic for component values). t a = 25c, unless otherwise noted. bold values indicate ? j ??& parameter conditions min . typ . max . unit buck current limit (out1 - out5) buck 1 current limit threshold see table 3 for i prog settings 3. 075 4.1 5.125 a buck 2 current limit threshold see table 3 for i prog settings 3.075 4.1 5.125 a buck 3 current limit threshold see table 3 for i prog settings 3.075 4.1 5.125 a buck 4 current limit threshold see table 3 for i prog settings 4.88 6.1 7.32 a buck 5 current limit threshold see table 3 for i prog settings 3.075 4.1 5.125 a gross high - side current limit [1 -5] with respect to buck [x] current limit 150 % zero cross threshold zero crossing detector 0 mv boost (v out6 ) boost output voltage (v out6 ) typical output voltage accuracy ( 11) includes load, line, and reference - 1.5% 1.5% % output voltage accuracy ( 11) -1% 1% % load regulation i out6 = 1.0ma to 200ma 0.2 % line regulation v in = 2.4v to 5.5v; i out6 = 10ma 0.2 % v out6 discharge current v in = 3.3v; v out6 = 12v 111 148 185 ma boost soft - start step duration soft - start 6 lsb ( 10, 12 ) 3.84 4 4.16 s/step boost internal mosfets low - side on- resistance v in = 3.3v; i sw1 = ? 100ma 160 p? low - side on- resistance v in = 5.0v; i sw1 = ? 100ma 140 p? boost disconnect mosfets disconnect switch on - resistance i pvin6o = 100ma; v in = 3.3v 90 p? disconnect switch current limit 5 a boost switching frequency switching frequency (pwm mode) 1.92 2 2.08 mhz minimum duty cycle 3 5 40 45 % maximum duty cycle 80 85 90 % boost current limit nmos current - limit threshold 2.24 a
micrel, inc. mic7400 march 3, 2015 14 revision 2.0 electrical characteristics ( 7 ) (continued) v in = av in = pv in (1 - 6) = 5.0v ; v out1 = 1.8v; v out2 = 1.1v; v out3 = 1.8v; v out4 = 1.05v; v out5 = 1.25v; v out6 = 12v (refer to the evaluation board schematic for component values). t a = 25c, unless otherwise noted. bold values indicate ? j ??& parameter conditions mi n . typ . max . unit i2c interface i2c interface (scl, sda) low level input voltage 0.4 v high level input voltage 1.2 v high level input current ? 2 00 0.01 200 na low level input current ? 2 00 0.01 200 na sda pull - down resistance 20 ? sda logic 0 output voltage i sda = 3ma 0.4 v clk, data pin capacitance 0.7 pf i2c interface timing ( 10 ) scl clock frequency standard mode 100 khz fast mode 400 high - speed mode ( 10) 3.4 mhz
micrel, inc. mic7400 march 3, 2015 15 revision 2.0 typical characteristic s 30 40 50 60 70 80 90 100 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) buck efficiency (ldcr = 0m?) vs. output current 0.8v 1.0v 1.2v 1.5v 1.8v v in = 3.3v l = 2.2h t a = 25 q c 3 30 40 50 60 70 80 90 100 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) buck efficiency (ldcr = 0m?) vs. output current 0.8v 1.0v 1.2v 1.5v 1.8v 2.5v 3.3v 3 v in = 5.0v l = 2.2h t a = 25 q c 30 40 50 60 70 80 90 100 0.0001 0.001 0.01 0.1 efficiency (%) output current (a) boost efficiency (12v) vs. output current 3.3v 5.0v l = 2.2h dcr = 116m ? samsung cig22h2r2mne t a = 25 q c 0.2 30 40 50 60 70 80 90 100 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) buck efficiency (ldcr = 40m?) vs. output current 0.8v 1.0v 1.2v 1.5v 1.8v v in = 5.0v l = 1.0h dcr = 40m ? samsung cigw252010gm1r0mne t a = 25 q c 3 30 40 50 60 70 80 90 100 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) buck efficiency (ldcr = 40m?) vs. output current 0.8v 1.0v 1.2v 1.5v 1.8v 2.5v 3.3v v in = 5.0v l = 1.0h dcr = 40m ? samsung cigw252010gm1r0mne t a = 25 ? c 3 -2.0% -1.5% -1.0% -0.5% 0.0% 0.5% 1.0% 1.5% 2.0% 0.0001 0.001 0.01 0.1 1 10 output voltage (v) output current (a) output voltage vs. output current -40 25 85 125 v in = 3.3v v out4 = 1.05v 30 40 50 60 70 80 90 100 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) buck efficiency (ldcr = 116m?) vs. output current 0.8v 1.0v 1.2v 1.5v 1.8v v in = 3.3vl = 2.2h dcr = 116m ? samsung cig22h2r2mne t a = 25 q c 30 40 50 60 70 80 90 100 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) buck efficiency (ldcr = 116m?) vs. output current 0.8v 1.0v 1.2v 1.5v 1.8v 2.5v 3.3v v in = 5.0v l = 2.2h dcr = 116m ? samsung cig22h2r2mne t a = 25 q c -1.0% -0.5% 0.0% 0.5% 1.0% -50 -25 0 25 50 75 100 125 output voltage (%) temperature ( c) output voltage vs. temperature v in = 3.3v v out4 = 1.05v i out4 = 2.5a
micrel, inc. mic7400 march 3, 2015 16 revision 2.0 typical characteristics (continued) 0.998 0.999 0.999 1.000 1.000 1.001 0.0001 0.001 0.01 0.1 1 output voltage (v) output current (a) buck output voltage (1.0v) vs. output current 3.3v 5v t a = 25 c -0.20% -0.15% -0.10% -0.05% 0.00% 0.05% 0.10% 0.15% 0.20% 0.0001 0.001 0.01 0.1 1 output voltage error (%) output current (a) buck output voltage regulation vs. output current 3.3v 5v t a = 25 c 0.000% 0.005% 0.010% 0.015% 0.020% 0.025% 0.030% 0.035% 2 3 4 5 6 output voltage error (%) input voltage (v) buck line regulation vs. input voltage i out = 1a t a = 25 c 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 0 1 2 3 output voltage (v) output current (a) dropout output voltage vs. output current v in = 3.3v v out = 3.3v l = 2.2h dcr = 116m ? samsung cig22h2r2mne t a = 25 ? c 0 50 100 150 200 250 300 0.0 1.0 2.0 3.0 4.0 5.0 supply current (a) input voltage (v) v in operating supply current vs. input voltage i out = 0a switching r pg = open r por = open t a = 25 ? c 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0.0 1.0 2.0 3.0 4.0 5.0 6.0 switchng frequency (mhz) input voltage (v) buck 2 switching frequency vs. input voltage v out2 = 1.1v i out2 = 0.5a t a = 25 c 0 1 2 3 4 5 6 0 1 2 3 4 5 6 current limit (a) output voltage (v) current - limit threshold vs. output voltage 5.1a 4.6a 4.1a 3.6a 3.1a 2.6a 2.1a 1.6a 1.1a 0 1 2 3 4 5 6 0 1 2 3 4 5 6 current limit (a) output voltage (v) output current limit vs. output voltage 5.1a 4.6a 4.1a 3.6a 3.1a 2.6a 2.1a 1.6a 1.1a 0 1 2 3 4 5 6 0 1 2 3 4 5 6 measured current limit (a) programmed current limit (a) programmed current limit vs. measured current limit v in = 5.0v v out = 1.05v
micrel, inc. mic7400 march 3, 2015 17 revision 2.0 functional characteristics
micrel, inc. mic7400 march 3, 2015 18 revision 2.0 functional characteristics (continued)
micrel, inc. mic7400 march 3, 2015 19 revision 2.0 functional characteristics (continued)
micrel, inc. mic7400 march 3, 2015 20 revision 2.0 functional characteristics (continued)
micrel, inc. mic7400 march 3, 2015 21 revision 2.0 functional characteristics (continued)
micrel, inc. mic7400 march 3, 2015 22 revision 2.0 functional characteristics (continued)
micrel, inc. mic7400 march 3, 2015 23 revision 2.0 functional characteristics (continued)
micrel, inc. mic7400 march 3, 2015 24 revision 2.0 mic7400 block diagram
micrel, inc. mic7400 march 3, 2015 25 revision 2.0 functional description the mic7400 is one of the industry?s m ost - advanced pmic designed for solid state d rives (ssd) on the market today. it is a multi - channel solution which offers software configurable soft - start, sequencing, and digital voltage control (dvc) that minimizes pc board area. these features usually require a pin for programming. however, t his approach makes the ic larger by increasing pin count, and also increases bom cost due to the external components. the following is a complete list of programmable features: ? buck output voltage (0.8v ? 3.3v/50mv steps) ? boost output voltage (7.0v ? 14v / 200mv steps) ? power - on - reset (2.25v ? 4 .25v/50mv steps) ? pow er - on - reset delay (5ms ? 160ms/ 5ms steps) ? power - up sequencing (6 time slots) ? power - up sequencing delay (0ms ? 7ms/1ms steps) ? soft - start (4s ? 1024s per step) ? buck current limit threshold ? (1.1 a to 6 .1a / 0.5a steps) ? boost current limit threshold ? (1.76 a to 2.6a/0.12a steps) ? boost pull - down (37ma to 148ma/37 ma steps) ? buck pull - grzq ? buck s tandby output voltage programmable ? boost s tandby output voltage programmable ? global power good masking t hese features give the system designer the flexibility to customize the mic7400 for their application. for example, v out1 curren t limit can be programmed to 4.1 a and v out2 can be set to 1.1 a. these outputs can be programmed to come up at the same time or 2 .0ms apart. in addition, in power - saving standby mode , the outputs can either be turned off or programmed to a lower voltage. with this programmability the mic7400 can be used in multiple platforms. the mic7400 buck regulators are adaptive on - time synchron ous step - down dc - to - dc regulators. they are designed to operate over a wi de input voltage range from 2.4 v to 5.5v and provide a regulated output voltage at up to 3.0 a of output current. an adaptive on - time control scheme is employed to obtain a constant sw itching frequency and to simplify the control compensation. the device includes an internal soft - start function which reduces the power supply input surge current at start - up by controlling the output voltage rise time. the mic7400 has a current - mode boo st regulator that can deliver up to 200ma of output current and only consumes 7 0 a of quiescent current. the 2.0mhz switching frequency allows small chip inductors to be used. programmable overcurrent sensing protects the boost from overloads and an output disconnect switch opens to protect against a short - circuit condition. soft - start is also programmable and controls both the rising and falling output. programmable buck soft - start control the mic7400 soft - start feature forces the output voltage to rise gr adually, which limits the inrush current during start - up. a slower output rise time will draw a lower input surge current. the soft - start time is based on the l east significant b it (lsb) of an internal dac and the speed of the ra mp rate, as shown in figure 1 . this illustrates the soft - start waveform for all five synchronous buck converters. the initial step starts at 150mv and each subsequent step is 50 mv. figure 1 . buck soft - start the output ramp rate (t ramp ) is s et by the soft - start registers. each output ramp rate can be individua lly set from 4s to 1024s, see table 1 for details.
micrel, inc. mic7400 march 3, 2015 26 revision 2.0 the soft - start time t ss can be calculated by equation 1 : ramp out ss t mv 50 v 15 . 0 v t ? ? ? ? ? ? ? = eq. 1 where : t ss = output r ise time v out = output voltage t ramp = output dwell time for example: s 264 t s 8 mv 50 v 15 . 0 v 8 . 1 t ss ss m = m ? ? ? ? ? ? ? = where : v out = 1.8v t ramp = 8.0 s table 1 . buck outputs default soft - start time ( default ) v out (v) t ramp ( s) t ss ( s) v out1 1.8 8 264 v out2 1.1 8 152 v out3 1.8 8 264 v out4 1.05 8 144 v out5 1.25 8 176 figure 2 shows the output of buck 1 ramping up cleanly, starting from 0.15v to its final 1.1v value. figure 2 . buck soft - start buck digital voltage control (dvc) the outpu t voltage has a 6 - bit control dac that can be programmed from 0.8v to 3.3v in 50mv increments. if the output is programmed to a higher voltage, then the output ramps up, as shown in figure 3 . figure 3 . buck dvc control ramp
micrel, inc. mic7400 march 3, 2015 27 revision 2.0 the ramp time is determined by e quation 2 : ramp init _ out out t mv 50 v v t ? ? ? ? ? ? ? ? ? = ? eq. 2 where: v out_init = initial output v oltage v out = final output v oltage t ramp = output d well time when the regulator is set in stand - by mode or programmed to a lower voltage, the n the output voltage ramps down at a rate determined by the output ramp rate (t ramp ), the output capacitance and the external load. small loads result in s low output voltage decay and heavy loads cause the decay to be controlled by the dac ramp rate . i n figure 4 , v out1 is switched to stand - by mode with an i2c command and then switched back to normal mode either by an i2c command or a low - to - high transition of the stby pin. in this case, the rise and fall times are the same due to a 1a load on v out1 . figure 4 . buck dvc control ramp programmable boost soft - start control the boost soft - start time is divided into two parts as shown in figure 5 . t1 is a fixed 367s delay starti ng from when the internal enable goes high. this delay gives enough time for the disconnect switch to turn on and bring the inductor voltage to v in before the boost is turned on. there is a 50s delay which is controlled by the parasitic capacitance (cgd) of the disconnect switch before the output starts to rise. after the t1 period, the dac output ramp starts, t2. the total soft - start time, t ss , is the sum of both periods. figure 6 displays the actual boost soft - start waveform. figure 5 . boost soft - start ramp figure 6 . boost soft - start
micrel, inc. mic7400 march 3, 2015 28 revision 2.0 ( ) ( ) s 16 v 2 . 0 v 4 . 1 v 12 2 t t v 2 . 0 v 4 . 1 v 2 t 2 t 1 t t ramp out ss m ? ? ? ? ? ? ? = ? ? ? ? ? ? ? = + = eq. 2 where: t1 = 367 s t2 = 848 s t ss = 367 s + 848 s = 1.215ms v out = output voltage t ramp = output dwell time = 16 s boost digital voltage control (dvc) the boost output control works the same way as the buck, except that the voltage steps are 200mv, see figure 7 . when the boost is programmed to a lower voltage the output ramps down at a rate determined by the output ramp rate (t ramp ), the output capacitance and the externa l load. during both the ramp up and down time, the power good output is blanked and if the power good mask bit is set to ?1?. figure 7 . boost dvc control ramp the ramp time can be computed using e quation 3 : ramp init _ out out t v 2 . 0 v v t ? ? ? ? ? ? ? ? ? = ? eq. 3 where : v out_init = initial output v oltage table 2 . boost output default soft - start time v out (v) t ramp ( s) t ss (ms) v out6 12 16 1.215 buck current limit the mic7400 buck regulators have high - side current limiting that can be varied by a 4 - bit code. if the regulator remains in current limit for more than seven consecutive pwm cycles, the output is latched off, the over - current status register bit is set to 1, the power - good status register bit is set to 0 and the global power good (pg) ou tput pin is pulled low. an over current fault on one output will not disable the remaining outputs. table 3 shows the current limit register settings verses output current. the current limit register setting is set at twice the maximum output current. table 3 . buck current l imit register settings i out (max) i prog binary hex 0.5a 1.1a 1111 f?h 1.0a 2.1a 1101 d?h 1.5a 3.1a 1011 b'h 2.0a 4.1a 1001 9'h 2.5a 5.1a 0111 7'h 3.0a 6.1a 0101 5'h the output can be turned back on by recycling the input power or by software control. to clear the overcurrent fault by software control, set the enable register bit to ?0? then clear the overcurrent faul t by setting the fault register bit to ?0?. this will clear the over - current and power good status registers. now the output can be re - enabled by setting the enable register bit to ?1?.
micrel, inc. mic7400 march 3, 2015 29 revision 2.0 during start - up sequencing if output 1 is still shorted, o utput s 2 through 4 will come up normally. once an over current condition is sensed, the n the fault register is set to ?1? and the start - up sequence will stop and no further outputs will be enabled. see figure 9 for default start - up sequence. boost current limit the boost current limit features cycle - by - cycle protection. the duty cycle is cut immediately once the current limit is hit. when the boost current limit is hit for five consecutive cycles, the fault signal is asserted and remains asser ted with the boost converter keeping on running until the boost is powered off. this protects the boost in normal overload conditions, but not in a short - to - ground case. for a short circuit to ground, the boost current limit will not be able to limit the inductor current. this short - circuit condition is sensed by the current in the disconnect switch. when the disconnect switch current limit is hit for four consecutive master clock cycles (2mhz), regardless if the boost is switching or not, both the disconn ect switch and boost are latched off automatically and the fault signal is asserted. the output can be turned back on by recycling the input power or by software control. to clear the overcurrent fault by software control, set the enable register bit to ?0? then clear the overcurrent faul t by setting the fault register bit to ?0?. global power good pin the global power - good output indicates that all the outputs are above the 91% limit after the power - up sequence is completed. once the power - up sequence is complete, the global power good output stays high unless an output falls below its power - good limit, a thermal fault occurs, the input voltage drops below the lower uvlo threshold or an output is turned off by setting the enable register bit to ?0? unles s th e pgood_mask[x] bit is set to ?1 ? (default) . a power - good mask bit can be used to control the glob al power good output. the power - good mask feature is programmed through the pgood_mask[x] registers and is use d to ignore an individual power - good fault. w hen masked , pgood_mask[x] bit is set to ?1?, an individual power good fault will not cause the global power good output to de - assert. if all the pgood_mask[x] bits are set to ?1?, then the power good output de - asserts as soon as the first output starts t o rise. the pgood_mask[x] bit of the last output must be set to ?0? to have the pg output stay low until the last output reaches 91% of its final value. the global power - good output is an open - drain output. a pull - up resistor can be connected to v in or v out . do not connect the pull - up resistor to a voltage higher than a v in . standard delay there is a programmable timer that is used to set the standard delay time between each time slot. the timer starts as soon as the previous time slot?s output power good goes high. when the delay completes, the regulators assigned to that time slot are en abled, see figure 8 . figure 8 . standa rd delay time power - up sequencing when power is first applied to the mic7400 , all i2c registers are lo aded with their default values from the eeprom. there is about a 1.5ms delay before the first regulator is enabled while the mic7400 goes through the init ialization process . the delay register?s stdel bits set the delay between powering up each regulator at initial power up. the sequencing registers allow the outputs to come up in any order. there are six time slots that an output can be configured to power up in. each time slot can be program m ed for up to six regulators to be turned on at once or none at all. figure 9 shows an example of this feature. v out4 is enabled in time slot 1. after a 1ms delay, v out2 and v out3 are enable at the same time in time slot 2. the 1ms is the standard delay for all of the outputs and can be programmed from 0ms to 7ms in 1ms. next, v out1 is powered up in time slot 3 and v out5 in time slot 4. there are no regulators program m ed for time slot 5. finally, v out6 is powered up in time slot 6. the global power good output, v pg , goes high as soon as the last output reaches 91% of its final value.
micrel, inc. mic7400 march 3, 2015 30 revision 2.0 figure 9 . hot plug ? v in rising vsl t pin the power - on reset threshold toggles between two diff erent ranges by driving the vsl t pin hig h or low. the lower range of 2.25v to 3.25 v is selected when the vsl t pin is tied to ground. the upper range, 3.25v to 4.25 v, is selected when the vsl t pin is tied to v in . programmable power - o n - reset (p o r) delay the por output pin provides the user with a way to let the soc know that the input power is failing. if the input voltage falls below the power - on reset lower threshold level, the por output immediately goes low. the lower threshold is set in the pordn register a nd the upper threshold uses porup register. the low - to - high por transition can be delayed from 5ms to 160ms in 5ms increments. this feature can be used to signal the soc that the power supplies are s table. the pordel register sets the delay of the por pin. the por delay starts as soon as the avin pin voltage rises above the power - on reset upper threshold limit. figure 10 shows the por operation. figur e 10 . por power - down sequencing when power is removed from v in , all the regulators try to maintain the output voltage until the input voltage falls below the uvlo limit of 2.35v as shown in fi gure 11 . figure 11 . hot un - plug ? v in falling
micrel, inc. mic7400 march 3, 2015 31 revision 2.0 stand - by mode in stand - by mode, efficiency can be improved by lowering the output voltage to the standby mode value or turning an output off completely. there are two registers used for setting the output voltage, normal - mode register and stand - by mode register. the def ault power - up voltages are set in the normal - mode registers. an i2c write command to the stby_ctrl_reg register or the stby pin can be used to set the mic 7400 into stand - by mode. figure 12 shows an i2c write command implementation. in stand - by mode, the output can be programmed to a lower voltage or turned completely off. when disabled, the output will be soft - discharged to zero if the pulld[1 - 6] regist er are set to 1. if pulld[x] = 0 the output drifts to pgnd at a rate determined by the load current and output capacitance. in stand - by , if an output is disabled, the global po wer good output is not affected when the pgood_mask[x] is set to logic 1. if the pgood_mask[x] is set to logic 0, then the global power good flag is pulled low. in figure 12 , all the pgood_mask[x] bits are set to logic 1. fi gure 12 . i 2 c stand - by mode resistive discharge to ensure a known output condition in stand - by mode, the output is actively discharged to ground if the output is disabled. setting the buck pull down register field pulld[1 - 5] = 1 c onnects a 90 pull down resistor from out[x] to pgnd [x] when the mic7400 is disabled. if pulld[x] = 0 the output drifts to pgnd at a rate determined by the load current and the output capacitance value . th e boost has a programmable pull - down current level from 37ma to 14 8 ma. in figure 13 , the top trace shows the normal pull down and the bottom trace is with the 90 pull - down. figure 13 . output pull - down resistance stby pin a pin - selectable stby input allow s the mic7400 to be placed into standby or normal mode. in standby mode, the individual regulator can be turned on or off or the output voltage can be set t o a different value. if the regulators are turned off, standby mode cuts the quiescent current by 23 a for each buck regulator and 70 a for the boost. figure 14 illustrates the stby pin operation. a low - to - high transition on the stby pin switches the output from stand by mode to normal mode. there is a 100s stby deglitch time to eliminate nuisance tripping then all the regulators are enabled at the same time and ramp up with their programmed ramp rates. a high - to - low transition on the stby pin switches the output from normal mode to stand by mode.
micrel, inc. mic7400 march 3, 2015 32 revision 2.0 figure 14 . stby -to - normal t ransition ( default ) safe start - up into a pre - biased output the mic 740 0 is designed for safe start - up into a pre - biased output. this prevents large negative inductor currents which can cause the output voltage to dip and excessive output voltage oscillations. a zero crossing comparator is used to detect a negative inductor current . if a negative inductor current is detected, the low - side synchronous mosfet functions as a diode and is immediately turned off. figure 15 shows a 1v output pre - bias at 0.5v at start - up, see v out4 trace. the inductor current, trace i l4 , is not allowed to go negative by more than 0.5a before the low - side switch is turned off. thi s feature prevents high negative inductor current flow in a pre - bias condition which can damage the ic. figure 15 . pre - biased output voltage buck regulator power dissipation the total power dissipation in a mic7400 is a combin ation of the five buck regulators and the boost dissipation. the buck regulators (out1 to out5) dissipation is approximately the switcher?s input power minus the switcher?s output power and minus the power loss in the inductor: p d_buck v in i in ? v out i out ? p l_loss eq. 4 while the boost power dissipation is estimated by e quation 5 : p d_boost v in i in ? v out x i out ? p l_loss ? v f i out eq. 5 although the maximum output current for a single buck regulator can be as much as 3 a , the mic7400 will thermal limit and will not support this high output current on all outputs at the same time. total power dissipation the total power dissipation in the mic7400 package is equal to the sum of t he power loss of each regulator: p d_total sum (p d_switchers ) eq. 6
micrel, inc. mic7400 march 3, 2015 33 revision 2.0 once the total power dissipation is calculated, the ic junction temperature can be estimated using equation 7 : t j(max) t a + p d_total t ja eq. 7 where: t j(max) = t he maximum junction temperature t a = t he ambient temperature ja = t he junction - to - ambient thermal resistance of the package ( 30 c/w) figure 16 shows the measured junction temperature versus power dissipation of the mic74 00 evaluation board. the actual junction temperature of the ic depends upon many factors. the significant factors influencing the die temperature rise are copper thickness in the pcb, the surface area available for convection heat transfer, air flow and po wer dissipation from other components, including inductors, socs and processor ics. it is good engineering practice to measure all power components temperature during the final design review using a thermal couple or ir thermometer , see the ? thermal measurements ? sub - section for details. figure 16 . power dissipation power derating the mic7400 package has a 2w power dissipation limit. to keep the ic junction temperature below a 125 c design limit, the output power has to be limit ed above an ambient temperature of 65 q c. figure 17 shows the power dissipation derating curve. figure 17 . power derating curve the maximum power dissipation of the package can be calculated by equation 8: ? ? 1 ? | ja a j(max) max) ( d t t p eq. 8 where: t j(max) = m aximum junction temperature (125c) t a = a mbient temperature ja = j unction- to - ambient thermal resistance of the package (30c/w). over t emperature fault an over temperature fault is triggered when the ic junction temperature reaches 160c. when this occurs , both the over temperature fault flag is set to ? 1 ? , the global p ower good output is pulled low and all the outputs are turned off. during the fault condition the i2c interface remains active and all registers values are maintained. when the die tempera ture decr eases by 20c the over temperature fault bit can be cleared. to clear the fault, either recycle power or write a logic ?0? to the over temperature fault register. once the fault bit is cleared, the outputs power up to their default values and are sequence d according to the time slot settings.
micrel, inc. mic7400 march 3, 2015 34 revision 2.0 input voltage ?hot plug? high - voltage spikes twice the input voltage can appear on the mic7401 pvin pins if a battery pack is hot - plugged to the input supply voltage connection as shown in figure 18 (trace 1). these spikes are due to the inductance of the wires to the battery and the very low inductance and esr of the ceramic input capacitors. this problem can be solved by placing a 150 f pos capacitor across the input terminals. figure 18 (trace 2) shows that the high - voltage spike is greatly reduced to a value below the maximum allowable input voltage rating. figure 18 . hot plug input voltage spike thermal measurements measuring the ic?s case temperature is recommended to ensure it is within its operating limits. although this might seem like a very elementary task, it is easy to get erroneous results. the most common mistake is to use the standard thermal c ouple that comes with a thermal meter. this ther mal couple wire gauge is large (typically 22 gauge) and behaves like a heatsink, resulting in a lower case measurement. two reliable methods of temperature measurement are a smaller thermal couple wire or an infrared thermometer. if a thermal couple wire is used, it must be constru cted of 36 gauge wire or higher (smaller wire size) to minimize the wire heat - sinking effect. in addition, the thermal couple tip must be covered in either thermal grease or thermal glue to make sure that the thermal couple junction is making good contact with the case of the ic. omega brand thermal couple (5sc - tt - k - 36- 36) is adequate for most applications. whenever possible, an infrared thermometer is recommended. the measurement sp ot size of most infrared thermometers is too large for an accurate reading on a small form factor ics. however, an ir thermometer from optris has a 1mm spot size, which makes it a good choice for measuring the hottest point on the case. an optional stand m akes it easy to hold the beam on the ic for long periods of time.
micrel, inc. mic7400 march 3, 2015 35 revision 2.0 timing diagrams normal power - up sequence for outputs the stdel register sets the delay between powering up of each regulator at initial power - up ( see power - up sequencing in figure 19 ) . once all the internal power good registers pgood[1 - 6] are all ? 1 ? , then the global pg pin goes high without delay if the pgood_mask[6] bit is set to ?0?. the pordel register sets the delay for the por flag pin. the por delay time starts as soon as the avin pin voltage rises above the system uvlo upper threshold set by the porup register. the por output goes low without delay if avin falls below the lower uvlo threshold set by the pordn regi ster. figure 19 . mic7400 power - up/ down
micrel, inc. mic7400 march 3, 2015 36 revision 2.0 standby ( stby ) pin (wake- up) an i2c write command to the stby_ctrl_reg register or the stby pin can be used to set the mic7400 into stand - by mode. the standby ( stby ) pin provides a hardware - specific manner in which to wake - up from stand - by mode and go into normal mode. figure 20 shows the stby pin operation. a low - to - high transition on the stby pin switches the output from stand - by mode to normal mode. there is a 100s stby degli tch time to eliminate nuisance tripping , then all the regulators are enabled at the same time and ramp up with their programmed ramp rates. figure 20 . mic7400 stby function ( default )
micrel, inc. mic7400 march 3, 2015 37 revision 2.0 evaluation board schematic sw4 out4 mic7400 c1 2.2f pvin1 l4 1.0h pgnd4 c14 22f pvin4 c13 10f sw3 out3 l3 2.2h pgnd3 c12 22f pvin3 c11 10f sw2 out2 l2 2.2h pgnd2 c10 22f pvin2 26 c9 10f l1 2.2h sw1 out1 pgnd1 c3 22f c2 10f pvin6 l6 2.2h pvin6o sw6 pgnd6 c6 10f pvin5 l5 2.2h sw5 out5 pgnd5 c8 22f c7 10f 31 30 avin vslt 15 14 13 por scl agnd sda 35 34 33 32 pg nc nc agnd 12 stby 16 r1 100k out6 c5 22f r6 499k d1 pmeg4002 27 29 28 25 24 23 22 21 20 19 17 18 2 1 3 36 4 5 7 6 8 9 11 10 r5 2k r3 2k r2 100k vin clk sda nc 4 3 2 r8 nf vin vin vin vin vin vin v out1 1.8v/0 .8a v out6 12v/0.2a v out5 1.25v/1.0a v out4 1.05v/3.0a v out3 1.8v/0.5a v out2 1.1v/0.5a r7 0 c4 10f pgnd pgnd pgnd gnd 1 pgnd vin vin pgnd pgnd pgnd r4 499k vin vslt vin stand - by stand - by por pg vslt tp14 vin pg vslt vin pgnd c15 150f +
micrel, inc. mic7400 march 3, 2015 38 revision 2.0 bill of materials item part number manufacturer description qty. c1 cl05 a 225ko5nqnc samsung ( 14 ) 2.2f/16v, ceramic, x5r, 0402, 0.8mm, 10% 1 c2, c7, c9, c11, c13 cl10a106mo8nqnc samsung 10f/16v, ceramic, x5r, 0603, 0.8mm, 20% 5 c4, c6 cl21a106kaynnne samsung 10f/25v, ceramic, x5r, 0805, 1.25mm, 20% 2 c3, c5, c8, c10, c12, c14 cl10a226mq8nune samsung 22f/6.3v, ceramic, x5r, 0603, 0.8mm, 20% 6 c15 eef - cx0j151xr panasonic 150f/6.3 v, pos capacitor, sp, 2 0% 1 d1 pmeg4002el nxp ( 15 ) 0.2a/40v, schottky, sod -882 1 r1, r2 rc1005f104cs samsung 100k?, resistor, 0402, 1% 3 r3, r5 rc1005f202cs samsung 2.0k?, resistor, 0402, 1% 2 r4, r6 rc1005f 4993cs samsung 499 k?, resistor, 0402, 1% 1 r7 rc1005j000cs samsung 0.00?, resistor, 0402, jumper 1 l1, l2, l3, l5, l6 cig22h2r2mne samsung 2.2h, 1.6a inductor, 116m?, 2520 1.2mm (max) 5 l4 cigw252010gm1r0mne samsung 1.0h, 3.3 a inductor , 40m?, 2520 1.0 mm (max) 1 u1 MIC7400YFL micrel ( 16) five - channel buck regulator plus one boost with hyperlight load ? and i 2 c control 1 notes: 14. samsung: www.samsung.com . 15. nxp: www.nxp.com . 16. micrel, inc.: www.micrel.com .
micrel, inc. mic7400 march 3, 2015 39 revision 2.0 pcb layout guidelines warning!!! to minimize emi and output noise, follow these layout recommendations. pcb l ayout is critical to achieve reliable, stable , and efficient performance. a ground plane is required to control emi and minimize the inductance in power, signal , and return paths. the following gu idel ines should be followed to e nsure proper operation: general ? most of the heat removed from the ic is due to the exposed pad (ep) on the bottom of the ic conducting heat into the internal ground planes and the ground plane on the bottom side of the board. us e at least 16 vias for the ep to ground plane connection. ? do not connect the pgnd and agnd traces together on the top layer. the single point connection is made on the layer 2 ground plane. ? do not put a via directly in front of a high current pin, sw, pgnd , or pvin. this will increase the trace resistance and parasitic inductance. ? do not place a via in between the input and output capacitor ground connection. put it to the in side of the output capacitor and in the way of the high di/dt current path. ? route all power traces on the top layer, as shown in the example layout. ? place the input capacitors first and put them as close as possible to the ic. ic ? the 2.2 f ceramic capacitor, which is connected to the avin pin, must be located right at the ic. the avin p in is very noise sensitive and placement of the capacitor is very critical. use wide traces to connect to the avin and agnd pins. ? the analog ground pin ( a gnd) must be connected directly to the ground planes. do not route the sgnd pin to the pgnd pad on the top layer. ? use fat traces to route the input and output power lines. ? use layer 5 as an input voltage power plane. ? layer 2 and the bottom layer ( layer 6) are ground planes. input capacitor ? a 10 f x5r or x7r dielectrics ceramic capacitor is recommended on each of the pvin pins for bypassing. ? place the input capacitors on the same side of the board and as close to the ic as possible. ? keep both the pvin pin and pgnd connections short. ? if possible, place vias to the ground plane close to the each input capacitor ground terminal, but not in the way of the high di/dit current path. ? use either x7r or x5r dielectric input capacitors. do not use y5v or z5u type capacitors. ? do not replace the ceramic input capacitor with any other type of capacitor. any type o f capacitor can be placed in parallel with the input capacitor. ? in ?hot - plug? applications, a tantalum or electrolytic bypass capacitor must be used to limit the over - voltage spike seen on the input supply with power is suddenly applied. inductor ? keep the inductor connection to the switch node (sw) short. ? do not route any digital lines underneath or close to the inductor. ? to minimize noise, place a ground plane underneath the inductor. output capacitor ? use a wide trace to connect the output capacitor groun d terminal to the input capacitor ground terminal. in the example layout, all input and output capacitor ground connections are place back - to - back. ? the out[1 - 6] trace should be separate from the power trace and connected as close as possible to the output capacitor. sensing a long high - current load trace can degrade the dc load regulation.
micrel, inc. mic7400 march 3, 2015 40 revision 2.0 proper termination of unused pins many designs will not require all six dc- to - dc output voltage s . in these case s , the unused pin must be connected to either v in or gnd . the schematic in figure 21 shows where to tie the unused pins and table 4 summarizes the connections. figure 21 . connections for unused pins table 4 . summarization of unused pin connections unused vin pgnd boost pvin6, pgin6o, vout6 pgnd6, sw6 buck pvin[x], vout[x} pgnd[6], sw[x] por por sw 4 out 4 mic 7400 c 1 2 . 2 f pvin 1 l 4 1 . 0 h pgnd 4 c 14 22 f pvin 4 c 13 10 f sw 3 out 3 l 3 2 . 2 h pgnd 3 c 12 22 f pvin 3 c 11 10 f sw 2 out 2 l 2 2 . 2 h pgnd 2 c 10 22 f pvin 2 26 c 9 10 f sw 1 out 1 pgnd 1 pvin 6 pvin 6 o sw 6 pgnd 6 pvin 5 l 5 2 . 2 h sw 5 out 5 pgnd 5 c 8 22 f c 7 10 f 31 30 avin vslt 15 14 13 por scl agnd sda 35 34 33 32 pg nc nc agnd 12 stby 16 r 1 100 k out 6 r 6 499 k 27 29 28 25 24 23 22 21 20 19 17 18 2 1 3 36 4 5 7 6 8 9 11 10 r 5 2 k r 3 2 k vin clk sda nc 4 3 2 r 8 nf vin vin vin vin vin vin v out 5 1 . 25 v / 1 . 0 a v out 4 1 . 05 v / 2 . 5 a v out 3 1 . 8 v / 0 . 5 a v out 2 1 . 1 v / 0 . 5 a r 7 0 pgnd gnd 1 pgnd vin vin pgnd pgnd pgnd r 4 100 k vin vslt vin stand - by stand - by por pg vslt tp 14 vin pg vslt vin pgnd c 15 150 f +
micrel, inc. mic7400 march 3, 2015 41 revision 2.0 pcb layout recommendations evaluation board top layer ? power component placement evaluation board top layer ? layer 1 (power routing layer)
micrel, inc. mic7400 march 3, 2015 42 revision 2.0 pcb layout recommendations (continued) evaluation board top layer ? layer 1 (power routing layer) evaluation board layer 2 (ground plane)
micrel, inc. mic7400 march 3, 2015 43 revision 2.0 pcb layout recommendations (continued) evaluation board top layer ? layer 3 (signal routing layer) evaluation board layer 4 (ground plane)
micrel, inc. mic7400 march 3, 2015 4 4 revision 2.0 pcb layout recommendations (continued) evaluation board layer ? layer 5 (v in plane) evaluation board bottom later ? layer 6 (ground plane)
micrel, inc. mic7400 march 3, 2015 45 revision 2.0 package information ( 17) and recommended landing pattern 36- pin 4.5mm 4.5mm fqfn ( fl ) note: 17. package information is correct as of the publication date. for updates and most current information, go to www.micrel.com .
micrel, inc. mic7400 march 3, 2015 46 revision 2.0 via layout design and layout constraints via layout design notes: dimensions in millimeters (mm) . this package is designed to be soldered to a thermal pad on the board. connect all ground planes together customers should contact their board fabrication site for recommended solder mask tolerance and via tenting recommendations f or vias placed in the thermal pad. 16 x , dia . 0 . 2 0 . 48 1 . 80 1 . 80 0 . 48
micrel, inc. mic7400 march 3, 2015 47 revision 2.0 appendix a i 2 c control register t he mic7400 i2c read/write registers are detailed here. during normal operation , the configuration data can be saved into non - volatile registers in eeprom by addressing the chip and wri ting to saveconfig key = 66?h. saving config data to eeprom takes time s o the external host should poll the mic7 400 and read the config bit [1] of eeprom ready register 01?h to determine the end of programming. all transactions start with a control byte sent from the i2c master device. the control byte begins with a start condi tion, followed by a 7 - bit slave address. the slave address is seven bits long followed by an eighth bit which is a data direction bit (r/w), a ? 0 ? indicates a transmission (write) and a ? 1 ? indicates a request for data (read). a data transfer is always ter minated by a stop condition that is generated by the master. serial port operation external host interface bidirectional i 2 c port capable of standard (up to 100kbits/s), fast (up to 400kbits/s), fast plus (up to 1mbit/s) and high speed (up to 3.4mbit/s) as defined in the i 2 c - bus specification . the mic7400 acts as an i 2 c slave when a ddressed by the external host . the mic7400 slave address uses a fixed 7 - bit code and is followed by an r/w bit which is part of the control word that is right after the start bit as shown in figure 22 in the device address column. the mic7400 can receive multiple data bytes after a single address byte and automatically increments its register pointer to block fill internal volatile memory. byte data is latched after individual bytes are received so multi - byte transfers could be corrupte d if interrupted mid - stream . no system clock is required by the digital core for i 2 c access from the external host (only the host scl clock is assumed). in order to prevent spurious operation of the i 2 c , if a start bit is seen, then any partial communicati on is aborted and new i 2 c data is allowed. start bit is when sda goes low when scl is high. stop bit is when sda goes high when scl is high. normal i 2 c exchange is shown in figure 22 . figure 22 . read/w rite protocol
micrel, inc. mic7400 march 3, 2015 48 revision 2.0 special host i 2 c commands the following commands are all 2 byte communications: byte1 = device address with write bit set, lsb = 0 byte2 = sp ecial key special keys ? saveconfig key = 66?h . saves the shadow register configuration data into eeprom registers 03?h thru 23 ?h. ? reset key = 6a?h . reload s only normal mode voltage and current limit settings then enable s the regulator to normal mode with no soft - start , no seque ncing, and no de lays. then clear s the standby register bit 6 in register 03?h . ? reload key = 6b?h . reloads all data from eeprom into the shadow registers . no other action s are performed , including soft - start, seque ncing, and delay. ? reboot ke y = 6c?h . turns all regulators off , reloads eeprom data into shadow registers, then re - sequences the regulators with the programmed soft - start and sequence delays. ? sequence key = 6d?h . turns all regulators off, restarts the sequencer including soft - start a nd sequence delays.
micrel, inc. mic7400 march 3, 2015 49 revision 2.0 appendix b register settings descriptions power good register (00?h) this register indicates when the regulators 1 ? 6 output voltage is above 91% of the target value. the mic7400 deglitches the input signal for 50s in o rder to prevent false events. the global pg pin indicator is functional ?and? of all the power good indicators during sequencing. once the power - up sequence is complete, the global power good output stays high unles s an output falls below its power - good limit, a thermal fault occurs, the input voltage drops below the lower uvlo threshold or an output is turned off by setting the enable register bit to ?0? if the pgood_mask[x] bit is set to ?0?. table 5 . power good status register register name pgood1 - 6_reg power good status register address 0x00? h field bit r/w default description pgood1 0 r 0 power good indicator for regulator 1 0 = buck not valid 1 = buck valid pgood2 1 r 0 power good indicator for regulator 2 0 = buck not valid 1 = buck valid pgood3 2 r 0 power good indicator for regulator 3 0 = buck not valid 1 = buck valid pgood4 3 r 0 power good indicator for regulator 4 0 = buck not valid 1 = buck valid pgood5 4 r 0 power good indicator for regulator 5 0 = buck not valid 1 = buck valid pgood6 5 r 0 power good indicator for regulator 6 0 = boost not valid 1 = boost valid reserved 6 r/w 0 not used reserved 7 r/w 0 not used
micrel, inc. mic7400 march 3, 2015 50 revision 2.0 eeprom - ready register (01?h) this register indicates the status of eeprom to external i2c host. the ready bit = 1 when the trim and config uration data have been loaded into core from eeprom after reset, reb oot or reload and the chip is ready for operation. [if the save 1 bit in register 04?h is read in as logic 1, the configuration registers will not be loaded from the eeprom memory and the ready bit will still get set indica ting that any startup procedure in vol ving the eeprom memory is complete. ] the ready bit will be set to 1 after loading or attempting to load trim and configuration data from eeprom into volatile memory. the trim data will always be loaded and if save1 bit in register 04?h is set to logic 0 , configuration data is also loaded. regardless of the save1 bit being set or not, after the loading opera tion the ready bit is set to 1. the config bit = 1 when the config uration data have been saved to eeprom after the saveconfi g code is issued from the host. if config=1 before the saveconfig code is issued, config will be cleared immediately and then will be set to logic 1 again once all configuration data is written to the eeprom memory. the calib bit = 1 when the trim data have been saved to eeprom aft er the savetrim code is issued from the host. if calib=1 before the savetrim code is issued, calib will be cleared immediately and then will be set to logic 1 again once all trim data is written to the eeprom memory. the eepread and eepwrite bits indicate if an eeprom read or write fault has occurred. these bits should be read and cleared prior to reloading data from the eeprom memory. table 6 . eeprom status register register name status_reg eeprom status register address 0x01 ? h field bit r/w default description ready 0 r 0 indicate ready for operation when the trim and configuration data has been loaded 0 = data not loaded 1 = chip ready config 1 r 0 indicate configuration saved to eeprom 0 = configuration not saved 1 = configuration saved calib 2 r 0 indicate trim data have been saved to eerom 0 = trim not saved 1 = trim saved reserved 3 r/w 0 not used reserved 4 r/w 0 not used reserved 5 r/w 0 not used ee pread 6 r/w 0 eeprom read 0 = no fault 1 = fault ee pwrite 7 r/w 0 eeprom write 0 = no fault 1 = fault
micrel, inc. mic7400 march 3, 2015 51 revision 2.0 fault registers (02?h) this register indicates the over - current flag for each regulator and one global overtemperature (ot). these register bits are set by an over current condition and reset by writing a logic ? 0 ? to each bit by the i2c host. if the fault condition persists, the bit will be set to logic ? 1 ? again immediately by the mic7400 after it is written to logic ? 0 ? by the host. table 7 . overcurrent status fault register register name fault_reg overc urrent status fault register address 0x02 ? h field bit r/w default description reg1oc 0 r/w 0 regulator 1 overc urrent 0 = no fault 1 = fault reg2oc 1 r/w 0 regulator 2 overc urrent 0 = no fault 1 = fault reg3oc 2 r/w 0 regulator 3 overc urrent 0 = no fault 1 = fault reg4oc 3 r/w 0 regulator 4 overc urrent 0 = no fault 1 = fault reg5oc 4 r/w 0 regulator 5 overc urrent 0 = no fault 1 = fault reg6oc 5 r/w 0 regulator 6 overc urrent 0 = no fault 1 = fault reserved 6 r/w 0 reserved ot 7 r/w 0 overt emperature 0 = no fault 1 = fault
micrel, inc. mic7400 march 3, 2015 52 revision 2.0 standby register (03?h) this register controls standby m ode operation. global stand - by mode can either be enabled by i2c or by changing the logic state of the stby input pin. global stand - by is controlled by the stby_modeb bit. when stby_modeb [6] = 1 then the regulators output voltages are set to their normal - mode output voltage settings, (05?h ? 0a?h) registers. when stby_modeb [6] = 0 then regulators output volta ges are set to the standby - mode output voltage sett ings, (0b?h ? 10?h) registers. if stby [1 - 6] register is set to logic ?0 ? , then the output is shut off in standby mode. the global power good flag is asserted when a n output is disabled unless the power g ood mask bit (pgood_mask[x]) is set to 1 . table 8 . standby register register name stby_ctrl_reg standby register address 0x03 ? h field bit r/w default description stby1 0 r/w 1 regulator 1 standby voltage control 0 = off 1 = on stby2 1 r/w 1 regulator 2 standby voltage control 0 = off 1 = on stby3 2 r/w 1 regulator 3 standby voltage control 0 = off 1 = on stby4 3 r/w 1 regulator 4 standby voltage control 0 = off 1 = on stby5 4 r/w 1 regulator 5 standby voltage control 0 = off 1 = on stby6 5 r/w 1 regulator 6 standby voltage control 0 = off 1 = on stby_modeb 6 r/w 1 global standby control 0 = all regulators in standby mode 1 = all regulators in normal mode reserved 7 r/w 0 not used
micrel, inc. mic7400 march 3, 2015 53 revision 2.0 enable/disable register (04?h) this register control s the enable/disable of each dc - to - dc regulators. when en(n) bit transitions from ? 0 ? to ? 1 ?, then the reg ulator(n) is enabled with soft - s tart unless the stby_mode b register bit in register 03?h is set to logic ? 0 ? . the configuration save bit ?save1? should be cleared by customer before saving config uration data to eeprom. this bit is used during power up to indicate via the status register (00?h) that config uration data has previously been stored. table 9 . enable register register name en_reg enable register address 0x04 ? h field bit r/w default description en1 0 r/w 1 regulator 1 on/off control bit 0 = off 1 = on en2 1 r/w 1 regulator 2 on/off control bit 0 = off 1 = on en3 2 r/w 1 regulator 3 on/off control 0 = off 1 = on en4 3 r/w 1 regulator 4 on/off control 0 = off 1 = on en5 4 r/w 1 regulator 5 on/off control 0 = off 1 = on en6 5 r/w 1 regulator 6 on/off control 0 = off 1 = on reserved 6 r/w 0 not used save1 7 r/w 0 save configuration 0 = configuration saved to eeprom 1 = not configuration saved to eeprom
micrel, inc. mic7400 march 3, 2015 54 revision 2.0 regulator output voltage setting normal m ode (05 ?h ? 09 ?h) one register for each regulator output ( out 1 ? out 5). sets output voltage of regulator for normal mode ope ration. table 10 . dvc registers for out[1 ? 5] register name out1 - 5_reg dvc registers for out [1 - 5] address out1 = 0x05 ? h out2 = 0x0 6? h out3 = 0x0 7? h out4 = 0x0 8? h out5 = 0x09 ? h field bit r/w default description out[1 -5] 5:0 r/w see table 2 output voltage setting of out[1 -5] dvc from 3.3 v to 0.8v in - 50mv steps 000000 = 3.30v 010000 = 2.50v 100000 = 1.70v 110000 = 0.90v 000001 = 3.25v 010001 = 2.45v 100001 = 1.65v 110001 = 0.85v 000010 = 3.20v 010010 = 2.40v 100010 = 1.60v 110010 = 0.80v 000011 = 3.15v 010011 = 2.35v 100011 = 1.55v 110011 = 0.80v 000100 = 3.10v 010100 = 2.30v 100100 = 1.50v 110100 = 0.80v 000101 = 3.05v 010101 = 2.25v 100101 = 1.45v 110101 = 0.80v 000110 = 3.00v 010110 = 2.20v 100110 = 1.40v 110110 = 0.80v 000111 = 2.95v 010111 = 2.15v 100111 = 1.35v 110111 = 0.80v 001000 = 2.90v 011000 = 2.10v 101000 = 1.30v 111000 = 0.80v 001001 = 2.85v 011001 = 2.05v 101001 = 1.25v 111001 = 0.80v 001010 = 2.80v 011010 = 2.00v 101010 = 1.20v 111010 = 0.80v 001011 = 2.75v 011011 = 1.95v 101011 = 1.15v 111011 = 0.80v 001100 = 2.70v 011100 = 1.90v 101100 = 1.10v 111100 = 0.80v 001101 = 2.65v 011101 = 1.85v 101101 = 1.05v 111101 = 0.80v 001110 = 2.60v 011110 = 1.80v 101110 = 1.00v 111110 = 0.80v 001111 = 2.55v 011111 = 1.75v 101111 = 0.95v 111111 = 0.80v 6 0 not used 7 0 not used
micrel, inc. mic7400 march 3, 2015 55 revision 2.0 boost regulator output voltage setting normal m ode (0a?h) sets output voltage of the boost regulator ( out 6) in normal mode operation. table 11 . dvc registers for out6 register name out6_reg dvc registers address 0x0a ? h field bit r/w default description out 6 5:0 r/w see table 2 dvc from 14v to 7v in 20 0mv decrements 000000 = 14.0v 010000 = 10.8v 100000 = 7.6v 110000 = 7.0v 000001 = 13.8v 010001 = 10.6v 100001 = 7.4v 110001 = 7.0v 000010 = 13.6v 010010 = 10.4v 100010 = 7.2v 110010 = 7.0v 000011 = 13.4v 010011 = 10.2v 100011 = 7.0v 110011 = 7.0v 000100 = 13.2v 010100 = 10.0v 100100 = 7.0v 110100 = 7.0v 000101 = 13.0v 010101 = 9.8v 100101 = 7.0v 110101 = 7.0v 000110 = 12.8v 010110 = 9.6v 100110 = 7.0v 110110 = 7.0v 000111 = 12.6v 010111 = 9.4v 100111 = 7.0v 110111 = 7.0v 001000 = 12.4v 011000 = 9.2v 101000 = 7.0v 111000 = 7.0v 001001 = 12.2v 011001 = 9.0v 101001 = 7.0v 111001 = 7.0v 001010 = 12.0v 011010 = 8.8v 101010 = 7.0v 111010 = 7.0v 001011 = 11.8v 011011 = 8.6v 101011 = 7.0v 111011 = 7.0v 001100 = 11.6v 011100 = 8.4v 101100 = 7.0v 111100 = 7.0v 001101 = 11.4v 011101 = 8.2v 101101 = 7.0v 111101 = 7.0v 001110 = 11.2v 011110 = 8.0v 101110 = 7.0v 111110 = 7.0v 001111 = 11.0v 011111 = 7.8v 101111 = 7.0v 111111 = 7.0v 6 0 not used 7 0 not used
micrel, inc. mic7400 march 3, 2015 56 revision 2.0 reg ulator voltage setting stby m ode (0b ?h ? 0f ?h) this register is used to s ets the output voltage of regulator s 1 ? 5 in stby m ode operation. table 12 . standby registers register name stby_ out1 - 5_reg standby dvc registers address out1 = 0x0 b? h out2 = 0x0 c? h out3 = 0x0 d? h out4 = 0x0 e? h out5 = 0x0 f? h field bit r/w default description sb_out[1 -5] 5:0 r/w see table 2 output voltage setting of out[1 -5] dvc from 3.3 v to 0.8v in - 50mv steps 000000 = 3.30v 010000 = 2.50v 100000 = 1.70v 110000 = 0.90v 000001 = 3.25v 010001 = 2.45v 100001 = 1.65v 110001 = 0.85v 000010 = 3.20v 010010 = 2.40v 100010 = 1.60v 110010 = 0.80v 000011 = 3.15v 010011 = 2.35v 100011 = 1.55v 110011 = 0.80v 000100 = 3.10v 010100 = 2.30v 100100 = 1.50v 110100 = 0.80v 000101 = 3.05v 010101 = 2.25v 100101 = 1.45v 110101 = 0.80v 000110 = 3.00v 010110 = 2.20v 100110 = 1.40v 110110 = 0.80v 000111 = 2.95v 010111 = 2.15v 100111 = 1.35v 110111 = 0.80v 001000 = 2.90v 011000 = 2.10v 101000 = 1.30v 111000 = 0.80v 001001 = 2.85v 011001 = 2.05v 101001 = 1.25v 111001 = 0.80v 001010 = 2.80v 011010 = 2.00v 101010 = 1.20v 111010 = 0.80v 001011 = 2.75v 011011 = 1.95v 101011 = 1.15v 111011 = 0.80v 001100 = 2.70v 011100 = 1.90v 101100 = 1.10v 111100 = 0.80v 001101 = 2.65v 011101 = 1.85v 101101 = 1.05v 111101 = 0.80v 001110 = 2.60v 011110 = 1.80v 101110 = 1.00v 111110 = 0.80v 001111 = 2.55v 011111 = 1.75v 101111 = 0.95v 111111 = 0.80v 6 0 not used 7 0 not used
micrel, inc. mic7400 march 3, 2015 57 revision 2.0 boost regulator output voltage setting stby m ode (10?h) sets output voltage of the boost regulator ( out 6) for stby mode operation. table 13 . standby dvc register for out6 register name stby _out6_reg dvc registers address 0x10 ? h field bit r/w default description sb_out6 5:0 r/w see table 2 dvc from 14v to 7v in 20 0mv decrements 000000 = 14.0v 010000 = 10.8v 100000 = 7.6v 110000 = 7.0v 000001 = 13.8v 010001 = 10.6v 100001 = 7.4v 110001 = 7.0v 000010 = 13.6v 010010 = 10.4v 100010 = 7.2v 110010 = 7.0v 000011 = 13.4v 010011 = 10.2v 100011 = 7.0v 110011 = 7.0v 000100 = 13.2v 010100 = 10.0v 100100 = 7.0v 110100 = 7.0v 000101 = 13.0v 010101 = 9.8v 100101 = 7.0v 110101 = 7.0v 000110 = 12.8v 010110 = 9.6v 100110 = 7.0v 110110 = 7.0v 000111 = 12.6v 010111 = 9.4v 100111 = 7.0v 110111 = 7.0v 001000 = 12.4v 011000 = 9.2v 101000 = 7.0v 111000 = 7.0v 001001 = 12.2v 011001 = 9.0v 101001 = 7.0v 111001 = 7.0v 001010 = 12.0v 011010 = 8.8v 101010 = 7.0v 111010 = 7.0v 001011 = 11.8v 011011 = 8.6v 101011 = 7.0v 111011 = 7.0v 001100 = 11.6v 011100 = 8.4v 101100 = 7.0v 111100 = 7.0v 001101 = 11.4v 011101 = 8.2v 101101 = 7.0v 111101 = 7.0v 001110 = 11.2v 011110 = 8.0v 101110 = 7.0v 111110 = 7.0v 001111 = 11.0v 011111 = 7.8v 101111 = 7.0v 111111 = 7.0v 6 0 not used 7 0 not used
micrel, inc. mic7400 march 3, 2015 58 revision 2.0 sequence register (11?h) each regulator can be assigned to start in any one of six sequencing slots (1 to 6). if starting in slot 1 , the regulator starts immediatel y. if starting in any other slot the regulator must wait for the pgood=1 flags of all regulators assigned to the preceding slot and then wait for the specified delay time (register 17?h) i.e. , all pgoo ds in preceding state flag then the delay timer is started and when delay completes the regulator is enabled. each regulator must delay its startup (after the appropriate preceding pgood flags) by the delay set in the delay register (17?h), unless the regu lator is assigned to sequence state 0. if all default enable bits = 0 the ic starts up, but no outputs are enabled. sequencing is only used during initial startup , and not used when outpu ts are enabled via i2c command. if outputs are enab led via i2c then soft - start is still active but start - up delays (timed from preceding pgood s ) are not. table 14 . sequence state 1 register register name seq1_reg sequence register address 0x11 ? h field bit r/w default description reg1sq 1 0 r/w 0 0 = no start 1 = regulator 1 will start in sequence state 1 reg2sq 1 1 r/w 0 0 = no start 1 = regulator 2 will start in sequence state 1 reg3sq 1 2 r/w 0 0 = no start 1 = regulator 3 will start in sequence state 1 reg4sq 1 3 r/w 1 0 = no start 1 = regulator 4 will start in sequence state 1 reg5sq 1 4 r/w 0 0 = no start 1 = regulator 5 will start in sequence state 1 reg6sq 1 5 r/w 0 0 = no start 1 = regulator 6 will start in sequence state 1 6 r/w 0 reserved 7 r/w 0 reserved
micrel, inc. mic7400 march 3, 2015 59 revision 2.0 table 15 . sequence state 2 register register name seq2_reg sequence register address 0x12 ? h field bit r/w default description reg1sq 2 0 r/w 0 0 = no start 1 = regulator 1 will start in sequence state 2 reg2sq 2 1 r/w 1 0 = no start 1 = regulator 2 will start in sequence state 2 reg3sq 2 2 r/w 1 0 = no start 1 = regulator 3 will start in sequence state 2 reg4sq 2 3 r/w 0 0 = no start 1 = regulator 4 will start in sequence state 2 reg5sq 2 4 r/w 0 0 = no start 1 = regulator 5 will start in sequence state 2 reg6sq 2 5 r/w 0 0 = no start 1 = regulator 6 will start in sequence state 2 6 r/w 0 reserved 7 r/w 0 reserved table 16 . sequence state 3 register register name seq3_reg sequence register address 0x13 ? h field bit r/w default description reg1sq 3 0 r/w 1 0 = no start 1 = regulator 1 will start in sequence state 3 reg 2 sq 3 1 r/w 0 0 = no start 1 = regulator 2 will start in sequence state 3 reg 3 sq 3 2 r/w 0 0 = no start 1 = regulator 3 will start in sequence state 3 reg 4 sq 3 3 r/w 0 0 = no start 1 = regulator 4 will start in sequence state 3 reg 5 sq 3 4 r/w 0 0 = no start 1 = regulator 5 will start in sequence state 3 reg 6 sq 3 5 r/w 0 0 = no start 1 = regulator 6 will start in sequence state 3 6 r/w 0 reserved 7 r/w 0 reserved
micrel, inc. mic7400 march 3, 2015 60 revision 2.0 table 17 . sequence state 4 register register name seq4_reg sequence register address 0x14 ? h field bit r/w default description reg1sq 4 0 r/w 0 0 = no start 1 = regulator 1 will start in sequence state 4 reg 2 sq 4 1 r/w 0 0 = no start 1 = regulator 2 will start in sequence state 4 reg 3 sq 4 2 r/w 0 0 = no start 1 = regulator 3 will start in sequence state 4 reg 4 sq 4 3 r/w 0 0 = no start 1 = regulator 4 will start in sequence state 4 reg 5 sq 4 4 r/w 1 0 = no start 1 = regulator 5 will start in sequence state 4 reg 6 sq 4 5 r/w 0 0 = no start 1 = regulator 6 will start in sequence state 4 6 r/w 0 reserved 7 r/w 0 reserved table 18 . sequence state 5 register register name seq5_reg sequence register address 0x15 ? h field bit r/w default description reg1sq 5 0 r/w 0 0 = no start 1 = regulator 1 will start in sequence state 5 reg 2 sq 5 1 r/w 0 0 = no start 1 = regulator 2 will start in sequence state 5 reg 3 sq 5 2 r/w 0 0 = no start 1 = regulator 3 will start in sequence state 5 reg 4 sq 5 3 r/w 0 0 = no start 1 = regulator 4 will start in sequence state 5 reg 5 sq 5 4 r/w 0 0 = no start 1 = regulator 5 will start in sequence state 5 reg 6 sq 5 5 r/w 0 0 = no start 1 = regulator 6 will start in sequence state 5 6 r/w 0 reserved 7 r/w 0 reserved
micrel, inc. mic7400 march 3, 2015 61 revision 2.0 table 19 . sequence state 6 register register name seq6_reg sequence register address 0x16 ? h field bit r/w default description reg1sq 6 0 r/w 0 0 = no start 1 = regulator 1 will start in sequence state 6 reg 2 sq 6 1 r/w 0 0 = no start 1 = regulator 2 will start in sequence state 6 reg 3 sq 6 2 r/w 0 0 = no start 1 = regulator 3 will start in sequence state 6 reg 4 sq 6 3 r/w 0 0 = no start 1 = regulator 4 will start in sequence state 6 reg 5 sq 6 4 r/w 0 0 = no start 1 = regulator 5 will start in sequence state 6 reg 6 sq 6 5 r/w 1 0 = no start 1 = regulator 6 will start in sequence state 6 6 r/w 0 reserved 7 r/w 0 reserved delay register (17?h) the stdel register sets the delay between powering up of each regulator at initial power up ( see figure 19 ) . once all the internal power good registers pgood[1 - 6] are all ? 1 ? , then the global pg pin goes high without delay. the pordel register sets the delay for the por flag pin. the por delay time starts as soon as avin pin voltage rises above the system uvlo upper threshold set by the porup register (21?h) . the por output goes low without delay if avin falls below the lower uvlo threshold set by the pordn register (22?h) . tabl e 20 . delay register register name delay_cntl_reg delay register address 0x17 ? h field bit r/w default description stdel 2:0 r/w 001 (1 ms) delay time from 0ms to 7ms in 1ms increment 000 = 0ms 010 = 2ms 100 = 4ms 110 = 6ms 001 = 1ms 011 = 3ms 101 = 5ms 111 = 7ms pordel 7:3 r/w 000 11 (20 ms) delay time from 5ms to 160ms in 5 ms increment 00000 = 5ms 01000 = 45ms 10000 = 85ms 11000 = 125ms 00001 = 10ms 01001 = 50ms 10001 = 90ms 11001 = 130ms 00010 = 15ms 01010 = 55ms 10010 = 95ms 11010 = 135ms 00011 = 20ms 01011 = 60ms 10011 = 100ms 11011 = 140ms 00100 = 25ms 01100 = 65ms 10100 = 105ms 11100 = 145ms 00101 = 30ms 01101 = 70ms 10101 = 110ms 11101 = 150ms 00110 = 35ms 01110 = 75ms 10110 = 115ms 11110 = 155ms 00111 = 40ms 01111 = 80ms 10111 = 120ms 11111 = 160ms
micrel, inc. mic7400 march 3, 2015 62 revision 2.0 soft - start registers (18 ?h ? 1a?h) when regulator(n) is turned on from either the enable register (04?h) in normal mode or from the standby register (03?h) in standby mode, the n the three reg(n)ss soft - start bits are used to control both the rising and falling ramp rate of the outputs . in normal mode, the outputs are stepped from the current regula tor voltage settings to a newly - programmed regulator voltage s etting o r to the default value. on power - up, the regulator voltage output is set to the lowest possible voltage setting which is 3f?h. the voltage regulator will chang e by one step or increment at a time. the amount of time between each step is controlled by the soft - start r egisters. table 21 details the amount of time fo r each encoded soft - start value. table 21 . soft- start register speed settings r/w default description ss_speed = 0 r/w 000 soft -s tart time from 4s to 512s 000 = 4s 010 = 16s 100 = 64s 110 = 256s 001 = 8s 011 = 32s 101 = 128s 111 = 512s ss_speed = 1 r/w 000 soft -s tart time from 8s to 1024s 000 = 8s 010 = 32s 100 = 128s 110 = 512s 001 = 16s 011 = 64s 101 = 256s 111 = 1024s table 22 . soft- start register out1 and out2 register name ss1 - 2_reg soft - start register for v out1 and v out2 address 0x18 ? h field bit r/w default description reg1ss 2:0 r/w 001 (8s) out1 soft - start time see table 1 9 for soft - start settings reg2ss 5:3 r/w 001 (8s) out2 soft - start time see table 1 9 for soft - start settings 6 r/w 0 reserved ss_speed 7 r/w 0 set the speed of the clock to slow or fast for different clock division , see table 1 9 . 0 = slow speed 1 = fast speed table 23 . soft- start register out3 and out4 register name ss3 - 4_reg soft - start register for v out 3 and v out 4 address 0x1 9 ? h field bit r/w default description reg 3 ss 2:0 r/w 001 (8 s ) out3 soft - start time see table 1 9 for soft - start settings reg 4 ss 5:3 r/w 001 (8 s ) out4 soft - start time see table 1 9 for soft - start settings 6 r/w 0 reserved 7 r/w 0 reserved
micrel, inc. mic7400 march 3, 2015 63 revision 2.0 table 24. soft - start register out5 and out6 register name ss5 - 6_reg soft - start register for v out 5 and v out 6 address 0x1 a? h field bit r/w default description reg 5 ss 2:0 r/w 001 (8s) out5 soft - start time see table 1 9 for soft - start settings reg 6 ss 5:3 r/w 010 (16s) out6 soft - start time see table 1 9 for soft - start settings 6 r/w 0 reserved 7 r/w 0 reserved current - limit (normal mode) registers (1b?h ? 1d?h) this register is use to se t the current limit for each dc - to - dc regulator in normal m ode operation . table 25 . current - limit register i out1 and i out2 register name ilimit_1 - 2_reg current - limit register for v out1 and v out2 address 0x1b ? h field bit r/w default description reg1cl 3:0 r/w 1001 (4.1a) normal current -l imit for regulator 1 from 8. 6 a to 1.1 a in 0.5 a de crements 0000 = 8.6 a 0100 = 6.6a 1000 = 4.6 a 1100 = 2.6 a 0001 = 8.1 a 0101 = 6.1a 1001 = 4.1 a 1101 = 2.1 a 0010 = 7.6a 0110 = 5.6a 1010 = 3.6 a 1110 = 1.6 a 0011 = 7.1a 0111 = 5.1 a 1011 = 3.1 a 1111 = 1.1 a reg2cl 7:4 r/w 1001 (4.1a) normal current - limit for r egulator 2 from 8.6 a to 1.1a in 0.5a de crements 0000 = 8.6 a 0100 = 6.6a 1000 = 4.6 a 1100 = 2.6 a 0001 = 8.1 a 0101 = 6.1a 1001 = 4.1 a 1101 = 2.1 a 0010 = 7.6a 0110 = 5.6a 1010 = 3.6 a 1110 = 1.6 a 0011 = 7.1a 0111 = 5.1 a 1011 = 3.1 a 1111 = 1.1 a
micrel, inc. mic7400 march 3, 2015 64 revision 2.0 table 26 . current - limit register i out3 and i out4 register name ilimit_3 - 4_reg current - limit register for v out3 and v out4 address 0x1c ? h field bit r/w default description reg3cl 3:0 r/w 1001 (4.1a) normal current -l imit for regulator 3 from 8.6 a to 1.1a in 0.5a de crements 0000 = 8.6 a 0100 = 6.6a 1000 = 4.6 a 1100 = 2.6 a 0001 = 8.1 a 0101 = 6.1a 1001 = 4.1 a 1101 = 2.1 a 0010 = 7.6a 0110 = 5.6a 1010 = 3.6 a 1110 = 1.6 a 0011 = 7.1a 0111 = 5.1 a 1011 = 3.1 a 1111 = 1.1 a reg4cl 7:4 r/w 0101 (6 .1a) normal current -l imit for regulator 4 from 8.6 a to 1.1a in 0.5a de crements 0000 = 8.6 a 0100 = 6.6a 1000 = 4.6 a 1100 = 2.6 a 0001 = 8.1 a 0101 = 6.1a 1001 = 4.1 a 1101 = 2.1 a 0010 = 7.6a 0110 = 5.6a 1010 = 3.6 a 1110 = 1.6 a 0011 = 7.1a 0111 = 5.1 a 1011 = 3.1 a 1111 = 1.1 a table 27 . current - limit register i out 5 and i out6 register name ilimit_5 - 6_reg current - limit register for v out5 and v out6 address 0x1d ? h field bit r/w default description reg5cl 3:0 r/w 1001 (4.1a) normal current -l imit for regulator 5 from 8.6 a to 1.1a in 0.5a de crements 0000 = 8.6 a 0100 = 6.6a 1000 = 4.6 a 1100 = 2.6 a 0001 = 8.1 a 0101 = 6.1a 1001 = 4.1 a 1101 = 2.1 a 0010 = 7.6a 0110 = 5.6a 1010 = 3.6 a 1110 = 1.6 a 0011 = 7.1a 0111 = 5.1 a 1011 = 3.1 a 1111 = 1.1 a reg6cl 6 :4 r/w 011 (2.24a) current limit from 2.6a to 1.78 a in 0.1 2 a decrements 000 = 2.6 a 010 = 2.36 a 100 = 2.12 a 110 = 1.88 a 001 = 2.48 a 011 = 2.24 a 101 = 2.00 a 111 = 1.76 a 7 r/w 0 0 = current limit on 1 = current limit off
micrel, inc. mic7400 march 3, 2015 65 revision 2.0 current - limit ( stby mode) registers (1e ? 20?h) this register is use d to set the current limit fo r each dc - to - dc regulator when in standby (stby) m ode operation . table 28 . standby current - limit register i out1 and i out2 register name stby_ilimit_1 - 2_reg standby current - limit register for v out1 and v out2 address 0x1e ? h field bit r/w default description sb1cl 3:0 r/w 1001 (4.1a) standby current l imit for regulator 1 from 8.6 a to 1.1a in 0.5a de crements 0000 = 8.6 a 0100 = 6.6a 1000 = 4.6 a 1100 = 2.6 a 0001 = 8.1 a 0101 = 6.1a 1001 = 4.1 a 1101 = 2.1 a 0010 = 7.6a 0110 = 5.6a 1010 = 3.6 a 1110 = 1.6 a 0011 = 7.1a 0111 = 5.1 a 1011 = 3.1 a 1111 = 1.1 a sb2cl 7:4 r/w 1001 (4.1a) standby current l imit for regulator 2 from 8.6 a to 1.1a in 0.5a de crements 0000 = 8.6 a 0100 = 6.6a 1000 = 4.6 a 1100 = 2.6 a 0001 = 8.1 a 0101 = 6.1a 1001 = 4.1 a 1101 = 2.1 a 0010 = 7.6a 0110 = 5.6a 1010 = 3.6 a 1110 = 1.6 a 0011 = 7.1a 0111 = 5.1 a 1011 = 3.1 a 1111 = 1.1 a table 29. standby current - limit register i out3 and i out4 register name stby_ilimit_3 - 4_reg standby current -l imit register for v out3 and v out4 address 0x1f ? h field bit r/w default description sb3cl 3:0 r/w 1001 (4.1a) standby current l imit for regulator 3 from 8.6 a to 1.1a in 0.5a de crements 0000 = 8.6 a 0100 = 6.6a 1000 = 4.6 a 1100 = 2.6 a 0001 = 8.1 a 0101 = 6.1a 1001 = 4.1 a 1101 = 2.1 a 0010 = 7.6a 0110 = 5.6a 1010 = 3.6 a 1110 = 1.6 a 0011 = 7.1a 0111 = 5.1 a 1011 = 3.1 a 1111 = 1.1 a sb4cl 7:4 r/w 0101 (6 .1a) standby current l imit for regulator 4 from 8.6 a to 1.1a in 0.5a de crements 0000 = 8.6 a 0100 = 6.6a 1000 = 4.6 a 1100 = 2.6 a 0001 = 8.1 a 0101 = 6.1a 1001 = 4.1 a 1101 = 2.1 a 0010 = 7.6a 0110 = 5.6a 1010 = 3.6 a 1110 = 1.6 a 0011 = 7.1a 0111 = 5.1 a 1011 = 3.1 a 1111 = 1.1 a
micrel, inc. mic7400 march 3, 2015 66 revision 2.0 table 30 . standby current - limit register i out5 and i out6 register name stby_ilimit_5 - 6_reg standby current - limit register for v out5 and v out6 address 0x20 ? h field bit r/w default description sb5cl 3:0 r/w 1001 (4.1a) standby current l imit for regulator 5 from 8.6 a to 1.1a in 0.5a de crements 0000 = 8.6 a 0100 = 6.6a 1000 = 4.6 a 1100 = 2.6 a 0001 = 8.1 a 0101 = 6.1a 1001 = 4.1 a 1101 = 2.1 a 0010 = 7.6a 0110 = 5.6a 1010 = 3.6 a 1110 = 1.6 a 0011 = 7.1a 0111 = 5.1 a 1011 = 3.1 a 1111 = 1.1 a sb6cl 6 :4 r/w 011 (2.24a) current limit from 2.6a to 1.78 a in 0.1 2 a decrements 000 = 2.6 a 010 = 2.36 a 100 = 2.12 a 110 = 1.88 a 001 = 2.48 a 011 = 2.24 a 101 = 2.00 a 111 = 1.7 6 a 7 r/w 0 0 = current limit on 1 = current limit off power - o n - reset (por) threshold voltage setting register (21?h and 22?h) this register is used to set the rising and falling threshold of power - on- reset ( por ) comparator. the por threshold voltage setting is based on the logic level of the vsl t pin in addition to the register bits. refer to table 20 for por time delay settings. table 31 . rising and falling power - on - reset threshold voltage settings rising and falling power - on - reset threshold voltage setting bit r/w default description vsclt = 0 4:0 r/w 00000 3.3v to 2.3v in 50mv de crements 00000 = 3 . 25v 01000 = 2.85 v 1 0000 = 2.45 v 11000 = 2. 25v 00001 = 3 . 20v 01001 = 2.80 v 10001 = 2.40 v 11001 = 2. 25v 00010 = 3.15 v 01010 = 2.75 v 10010 = 2.35 v 11010 = 2. 25v 00011 = 3.10 v 01011 = 2.70 v 10011 = 2.30 v 11011 = 2. 25v 00100 = 3.05 v 01100 = 2.65 v 10100 = 2.25 v 11100 = 2. 25v 00101 = 3.00 v 01101 = 2.60 v 10101 = 2. 25v 11101 = 2. 25v 00110 = 2.95 v 01110 = 2.55 v 10110 = 2. 25v 11110 = 2. 25v 00111 = 2.90 v 01111 = 2.50 v 10111 = 2. 25v 11111 = 2. 25v vsclt = 1 4:0 r/w 00000 4 .3v to 3.3v in 50mv de crements 00000 = 4.25 v 01000 = 3.85 v 10000 = 3. 45v 11000 = 3. 25v 00001 = 4.20 v 01001 = 3. 80v 10001 = 3. 40v 11001 = 3. 25v 00010 = 4.15 v 01010 = 3. 75v 10010 = 3. 35v 11010 = 3. 25v 00011 = 4.10 v 01011 = 3. 70v 10011 = 3. 30v 11011 = 3. 25v 00100 = 4.05 v 01100 = 3. 65v 10100 = 3. 25v 11100 = 3. 25v 00101 = 4.00 v 01101 = 3. 60v 10101 = 3. 25v 11101 = 3. 25v 00110 = 3.95 v 01110 = 3. 55v 10110 = 3. 25v 11110 = 3. 25v 00111 = 3.90 v 01111 = 3.5 0 v 10111 = 3. 25v 11111 = 3. 25v the three most significant bits [7:5] in registers 21?h and 22?h are used t o mask the output voltage power - good flag after the start - up sequenced is finished.
micrel, inc. mic7400 march 3, 2015 67 revision 2.0 table 32. power - on - reset rising threshold v oltage setting register (21?h) register name poruo _reg power - on - reset falling threshold address 0x2 1? h field bit r/w default description porup 4:0 r/w 01011 (2.7v) see table 28 pgood_mask 1 5 r/w 1 0 = do not mask pgood 1 1 = mask pgood 1 pgood_mask 2 6 r/w 1 0 = do not mask pgood 2 1 = mask pgood 2 pgood_mask 3 7 r/w 1 0 = do not mask pgood 3 1 = mask pgood 3 table 33. power - on - reset falling threshold voltage setting register (22?h) register name pordn_reg power - on - reset falling threshold address 0x2 2? h field bit r/w default description pordn 4:0 r/w 01101 (2.6v) see table 28 pgood_mask4 5 r/w 1 0 = do not mask pgood4 1 = mask pgood4 pgood_mask5 6 r/w 1 0 = do not mask pgood5 1 = mask pgood5 pgood_mask6 7 r/w 1 0 = do not mask pgood6 1 = mask pgood6 pull - down when disabled register (23?h) this register is use d to set the preferen ce of enabling/disabling a pull - down fe t when the dc - to - dc regulators are disabled. the pull - down value for buck regulators 1 ? 5 is 90 ?7khsxoo - down current value for the boost regulator 6 is programmable. table 34 . pull - down when disabled register register name pulldn1 - 6_reg pull - down when disabled register address 0x23 ? h field bit r/w default description pulld1 0 r/w 0 enable/disable the pull - down on regulator 1 when power down 0 = no pull down 1 = pull - down pulld2 1 r/w 0 enable/disable the pull - down on regulator 2 when power down 0 = no pull - down 1 = pull - down pulld3 2 r/w 0 enable/disable the pull - down on regulator 3 when power - down 0 = no pull - down 1 = pull down pulld4 3 r/w 0 enable/disable the pull - down on regulator 4 when power down 0 = no pull - down 1 = pull - down pulld5 4 r/w 0 enable/disable the pull - down on regulator 5 when power - down 0 = no pull - down 1 = pull - down pulld 6c 6:5 r/w 00 sets boost pull - down current level 00 = 148 ma 01 = 111 ma 10 = 74 ma 11 = 37 ma pulld 6 7 r/w 0 enable/dis able the pull - down on regulator 6 when power - down 0 = no pull - down 1 = pull - down
micrel, inc. mic7400 march 3, 2015 68 revision 2.0 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474- 1000 web http://www.micrel.com micrel, inc. is a leading global manufacturer of ic solutions for the worldwide high - performance linear and power, lan, and timing & communications markets. the company?s products include advanced mixed - signal, analog & power semiconductors; high - performan ce communication, clock management, mems - based clock oscillators & crystal - less clock generators, ethernet switches, and physical layer transceiver ics. company customers include leading manufacturers of enterprise, consumer, industrial, mobile, telecommunications, automotive, and comp uter products. corporation headquarters and state - of - the - art wafer fabric ation facilities are located in san jose, ca, with regional sales and support offices and advanced technology design centers situated throughout the americas, europe, and asia. additionally, the company maintains an extensive network of distributors and r eps worldwide. micrel makes no representations or warranties with respect to the accuracy or completeness of the inf ormation furnished in this data sheet. this information is not intended as a warranty and micrel does not assume responsibility for its use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. e xcept as provided in micrel?s terms and conditions of sale for such products, micrel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or use of micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright , or other intellectual property right. micrel products are not designed or authorized for use as components in life support appliances, devices or systems wher e malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchaser?s use or sale of micrel products for use in life support appliances, devices or systems is a purchaser?s own risk a nd purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2014 micrel, incorporated.

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